Browse Prior Art Database

Direct Memory Access Controller Capable of Auto-Triggering the Transfer of Multiple Data Blocks

IP.com Disclosure Number: IPCOM000122957D
Original Publication Date: 1998-Jan-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 189K

Publishing Venue

IBM

Related People

Olsen, CM: AUTHOR [+2]

Abstract

The problem with current host based Direct Memory Access (DMA) controllers, such as the Intel* 8237A, is that the controller can only be programmed to transmit a single block of data at a time. Not until the DMA controller has completed the transfer of the data block can the controller be programmed to send another data block. This has ramifications for transferring data packets onto a network at high speeds through an adapter that takes advantage of the DMA controller to transfer data packets from main memory to the adapters First In First Out (FIFO) or local memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 32% of the total text.

Direct Memory Access Controller Capable of Auto-Triggering the Transfer
of Multiple Data Blocks

      The problem with current host based Direct Memory Access (DMA)
controllers, such as the Intel* 8237A, is that the controller can
only be programmed to transmit a single block of data at a time.  Not
until the DMA controller has completed the transfer of the data block
can the controller be programmed to send another data block.  This
has ramifications for transferring data packets onto a network at
high speeds through an adapter that takes advantage of the DMA
controller to  transfer data packets from main memory to the adapters
First In First Out  (FIFO) or local memory.

      To transfer data from memory to an Industrial Standard
Architecture (ISA) Input/Output (I/O) device in a fashion that
utilizes system hardware resources and imposes the smallest load on
the system,  an I/O device can take advantage of the system DMA
controller to transfer  data from main memory to the device and from
the device to main memory.  The DMA controller allows the transfers
to be performed in a number of ways.  The device driver configures
the DMA controller in a number of ways: 1) it sets the transfer mode
of the DMA controller, 2) it sets the direction of the data transfer
and 3) it writes the starting address and size of the data block to
be transferred into a couple of registers.  The actual data transfers
may be gated by the adapter itself in a number of different ways
depending on the mode of the DMA controller.  For example, in the
"Demand Transfer" mode the I/O device adjusts the flow of data by
toggling the DMA Request (DREQ)  line on the system bus.  Upon the
transfer of the last data byte, the device makes the DREQ inactive to
stop the flow of data.  In order for  the DMA controller to be set up
for the next transfer, the I/O device issues a "Prepare Next Data
Block"-interrupt to the device driver. The  device driver services
the interrupt, programs the DMA controller and informs the I/O device
that the next data block is ready.
  -------------------------------------------------------
  | Transmission Rate | Packet Size | Transmission Time |
  |      (Mbps)       |   (bytes)   |      (usec)       |
  -------------------------------------------------------
  |         4         |    2048     |       4096        |
  |         4         |     512     |       1024        |
  |         4         |     128     |        256        |
  |        10         |     128     |        102        |
  |        10         |      64     |         51        |
  -------------------------------------------------------

Table Transmission time for selected packet sizes at 4 & 10 Mbps

      The consequence of the interrupt...