Browse Prior Art Database

Support of 2.0 Compliant Peripheral Component Interconnect (PCI) Adapters in 2.1 Compliant Systems

IP.com Disclosure Number: IPCOM000122985D
Original Publication Date: 1998-Mar-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 103K

Publishing Venue

IBM

Related People

Guthrie, GL: AUTHOR [+4]

Abstract

A method for allowing PCI Host bridges and PCI-PCI bridges that are compliant with the Revision 2.1 PCI Local Bus Specification to be more tolerant of certain adapters that are compliant with the Revision 2.0 PCI Local Bus Specification.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Support of 2.0 Compliant Peripheral Component Interconnect (PCI)
Adapters in 2.1 Compliant Systems

      A method for allowing PCI Host bridges and PCI-PCI bridges that
are compliant with the Revision 2.1 PCI Local Bus Specification to be
more tolerant of certain adapters that are compliant with the
Revision 2.0 PCI Local Bus Specification.

      Some PCI masters that were designed to the Revision 2.0 PCI
Local Bus Specification may cause livelocks and resulting performance
problems in systems designed to be compliant to the Revision 2.1 PCI
Local Bus Specification.

      This publication describes a solution to the problem described
above by defining means to allow 2.1 Compliant PCI Host Bridges and
PCI-PCI bridges to be more tolerant of certain 2.0 compliant
adapters.

      The Revision 2.1 PCI Local Bus Specification clearly
defines a number of requirements for 2.1 compliant devices to avoid
deadlocks/livelocks.  Some of these requirements were not defined in
the 2.0 PCI Local Bus Specification.  The following are examples of
such requirements.

      One 2.1 requirement is that the master is required to continue
to repeat read requests that are Retried, until the Read completes.
If the original transaction is never completed, a deadlock may
occur.  Another 2.1 requirement is that a device is not allowed to
make the acceptance (posting) of a memory write transaction as a
target contingent on the prior completion of a transaction as a
master, otherwise a deadlock may occur.  Another requirement
(optional in the 2.1 Local Bus Specification) is that a subsequent
Delayed Read Completion (DRC) should be allowed to pass a previous
DRC, otherwise a deadlock can occur.

      It is important to allow progress of transactions through a
bridge to avoid thrashing.  This can be accomplished by providing a
progress bit.  Read Completion Data when stored in a buffer can be
covered by resetting a progress bit for that transaction.  When the
master attempts that read access again and the master obtains at
least one byte or word of data in that buffer, then the progress bit
can be set and that data can be cast out.  By holding the data until
the master gets at least some data before that buffer is cast out,
this allows "progress" and avoid thrashing of the read completion
buffers.

      It also is important for a 2.1 Compliant PCI Host Bridge and/or
a PCI-PCI bridge to be tolerant of certain 2.0 compliant devices that
may not be compliant to the 2.1 PCI Local Bus requirements listed
above.  Means to add a degree of tolerance of these 2.0 compliant
devices is to provide a timer or counter to limit the time that the
bridg...