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Enhanced Clocking Scheme for Multifunction CORE Methodology

IP.com Disclosure Number: IPCOM000122995D
Original Publication Date: 1998-Mar-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Galambos, T: AUTHOR [+3]

Abstract

CORE macro is defined as a unique cell within the ASIC technology library which can be used by the ASIC developer. The CORE may contain several parts (CHIPLETS) which are connected to each other by external wiring done by the user. In order to maintain the correct timing criteria assumed by the CORE developer, the user must keep the same loading on the interface IO pins including the clock inputs.

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This is the abbreviated version, containing approximately 83% of the total text.

Enhanced Clocking Scheme for Multifunction CORE Methodology

      CORE macro is defined as a unique cell within the ASIC
technology library which can be used by the ASIC developer.  The CORE
may contain several parts (CHIPLETS) which are connected to each
other by external wiring done by the user.  In order to maintain the
correct timing criteria assumed by the CORE developer, the user must
keep the same loading on the interface IO pins including the clock
inputs.

A typical implementation of a CORE contains a central unit surrounded
by several other chiplets.  The central chiplet (ENGINE) contains the
clock generation logic (clock splitter).  The rest of the chiplets
are connected to the ENGINE.  There may by several options to
configure this CORE usage.  The user may choose to connect a part of
the total chiplets provided or all of them.  The clocking scheme
should be immuned  from the fact that different number of chiplets
are connected to the same  ENGINE.

Another requirement for the user of the CORE is maintaining the same
delay for all the internal latches from the clock input.  i.e, the
delay between the clock input and the internal latch in the ENGINE
should be equal to the delay between the clock input and the internal
latch in the chiplet

The enhanced clocking scheme provides a simple way to build a clock
tree for any type of CORE structure.  The ENGINE which contains the
clock unit (clock splitter) will drive a set of buffers (as the
maximum number...