Browse Prior Art Database

Using Interrupts to Automatically Verify Hardware Functions in a Simulation Model

IP.com Disclosure Number: IPCOM000123010D
Original Publication Date: 1998-Apr-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Currier, GR: AUTHOR [+3]

Abstract

A method of automatic verification of hardware functions within a simulation model is disclosed. An interrupt/interrupt acknowledge scheme is implemented to perform the automatic checking of signals within the hardware model.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 66% of the total text.

Using  Interrupts to Automatically Verify Hardware Functions in a
Simulation Model

      A method of automatic verification of hardware functions within
a simulation model is disclosed.  An interrupt/interrupt acknowledge
scheme is implemented to perform the automatic checking of signals
within the hardware model.

      Disclosed is a method of using an Interrupt/Interrupt
Acknowledge scheme to automatically verify hardware function during
simulation.  Examples of the types of functional verification that
can be monitored   for Scan Controller hardware verification are as
follows: Scan Operation completion, appropriate scan ring selects,
clock commands, LBIST (Logic Built-In Self-Test) completion and ABIST
(Array Built-In Self-Test) completion and other specific "Test
Controller" functions.  When the Interrupt Model determines that one
of these operations have occurred, the appropriate information is
stored into an interrupt information register (labeled Trigger in the
figure) and an interrupt is asserted.  Another piece of the solution
involves a Test Verification Model that monitors the interrupt
activity and returns either an Interrupt Acknowledge or Error
indication to the  testcase depending upon whether the interrupt was
expected.  The testcase  writer has the capability of determining
which interrupts to expect and  what type of information to expect in
the Interrupt Information register  (Trigger) when the interrupt
occurs (i.e., states of other...