Browse Prior Art Database

Preventing Instruction Register Status Aliasing in a Test Access Port Controller

IP.com Disclosure Number: IPCOM000123011D
Original Publication Date: 1998-Apr-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 43K

Publishing Venue

IBM

Related People

Currier, GR: AUTHOR [+2]

Abstract

A method of preventing IEEE 1149.1 (JTAG) instruction register status information from being misinterpreted as an instruction is disclosed. Such aliasing is possible anytime the Update-Instruction Register (IR) test access port (TAP) state is entered without first passing through the Shift-IR state.

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Preventing Instruction Register Status Aliasing in a

Test

Access

Port

Controller

      A method of preventing IEEE 1149.1 (JTAG) instruction register
status information from being misinterpreted as an instruction is
disclosed.  Such aliasing is possible anytime the Update-Instruction
Register (IR) test access port (TAP) state is entered without first
passing through the Shift-IR state.

      The Test Access Port (TAP) state machine, defined in the IEEE
1149.1 (JTAG) specification, allows a state transition sequence that
results in the Instruction Register (IR) status information being
interpreted as a valid instruction.  The format of the IR Status is
free-form, meaning that many status bit patterns may alias to valid,
and potentially destructive JTAG machine instructions.  This can
result in extended test time due to misread scan/system data, false
manufacturing test failures, or machine failure requiring a re-IPL to
recover system operation if the TAP port is used functionally in the
system.  The problem can occur due to noise on the TMS or TCK signal
lines, or due to a programming defect in the TAP sequence.

      A "Serialized IR Status Indicator" (SIRSI) latch was added
which is set when the Capture-IR state is entered.  This latch is
reset when the Shift-IR state is entered.  The loading and subsequent
execution of the parallel portion of the JTAG instruction register is
blocked while the SIRSI latch is set.  If the errant state machine
sequence (...