Browse Prior Art Database

How to Merge Clock Gating in a Scan Controller

IP.com Disclosure Number: IPCOM000123024D
Original Publication Date: 1998-Apr-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 27K

Publishing Venue

IBM

Related People

Currier, GR: AUTHOR [+2]

Abstract

The IEEE 1149.1 (JTAG) Specification requires the definition of a bypass register. By increasing the width of the bypass register, this register can be re-used as an interface to read/write multiple test data registers (TDRs). The number of gated scan paths is reduced from "N" to one (only the bypass register needs TCK gated clocks). The bypass register also serves as a common isolation register for TDRs that cross clock domain boundaries.

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How to Merge Clock Gating in a Scan Controller

      The IEEE 1149.1 (JTAG) Specification requires the definition of
a bypass register.  By increasing the width of the bypass register,
this register can be re-used as an interface to read/write multiple
test data  registers (TDRs).  The number of gated scan paths is
reduced from "N" to one (only the bypass register needs TCK gated
clocks).  The bypass register also serves as a common isolation
register for TDRs that cross  clock domain boundaries.

      In the figure below, all TDRs (except bypass) receive
functional clocks while TDR(n) is being scanned via JTAG.  TDR(n)
data is stable during the scan, updated only during TAP=updateDR,
thus TDR(x)  does not observe intermediate scan data.  Multiple TDRs
"share" bypass  as a conduit for JTAG scans.