Browse Prior Art Database

Parallel Inter-integrated Circuit (I2C) Bus Expander

IP.com Disclosure Number: IPCOM000123027D
Original Publication Date: 1998-Apr-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Ku, Y: AUTHOR [+2]

Abstract

Disclosed is a scheme to expand the I2C bus, a simple two-wire serial bus to access more slave-only I2C devices using only 1 primary I2C address.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Parallel Inter-integrated Circuit (I2C) Bus Expander

      Disclosed is a scheme to expand the I2C bus, a simple two-wire
serial bus to access more slave-only I2C devices using only 1 primary
I2C address.

      Detailed herein is a way to expand the I2C bus to accommodate
up to 1024 slave-only devices.

      If all 1025 devices (dev 0-1023 and the I/O expander) were
connected to the primary I2C bus, then we would need 1025 dedicated
I2C addresses in order to access the devices.  But this is impossible
given the limitation of the I2C standard which only allows a maximum
of 256 distinct primary addresses.

      The scheme above only uses 1 primary I2C address for the I/O
expander yet provide full read/write capability for up to 1024
devices.  Up to 4 devices can be accessed in parallel at a time.  The
reason that this is possible is that the I/O expander port pins can
be used as either input or output pins which are completely under
control of software.

      For loading purposes, one can insert buffers on SCL line to
drive devices.  Timing consideration is also not a problem because
software can generate I2C read/write cycles to devices by
reading/writing the PCF8574 ports.