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Pre-Discharge Technique to Improve Noise Immunity on Silicon-on- Insulator (SOI) Domino Circuits

IP.com Disclosure Number: IPCOM000123053D
Original Publication Date: 1998-Apr-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 162K

Publishing Venue

IBM

Related People

Durham, CM: AUTHOR [+2]

Abstract

This paper describes an easy method for improving noise immunity on CMOS domino circuits in SOI technologies. Mostly applicable to circuits being migrated from a bulk-CMOS to an SOI-CMOS technology, it consists of changing the internal precharge to ground instead of the supply, thus reducing the initial body potential and increasing the threshold.

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Pre-Discharge Technique to Improve Noise Immunity on Silicon-on-
Insulator (SOI) Domino Circuits

      This paper describes an easy method for improving noise
immunity on CMOS domino circuits in SOI technologies.  Mostly
applicable to circuits being migrated from a bulk-CMOS to an SOI-CMOS
technology, it consists of changing the internal precharge to ground
instead of the supply, thus reducing the initial body potential and
increasing the threshold.

      As processors have continually increased their speed
requirements, designers have turned to more complex circuits to keep
up with the demand, usually dynamic styles.  However, these styles
are harder to implement and, typically, fail more often after
manufacture due to design errors.

      One popular style in industry is "domino", an example of which
is shown in Fig 1.  Domino circuits in CMOS-bulk technology can
perform better if parasitic capacitance at internal nodes between
n-stack device  is discharged during the precharge cycle.  However,
due to charge sharing  effects this cannot generally be done.

      For example, if during the evaluate cycle of the circuit in
Fig. 1 nodes "q0" and "q1" are discharged, signals "y<0>" and "y<1>"
remain low, and signals "x<0>", "x<1>" and "x<2>" transition high,
then the parasitic capacitors on nodes "q0" and "q1" will share or
redistribute the charge stored on the capacitance of node "int".  If
the sharing event is sufficient enough to drop the signal value of
node "int" below the switching voltage of the inverter created by the
pmos/nmos device pair, then the output "out" will errantly switch.
Note that this switching event is incorrect because the logic
circuitry.  That is, node "out" should go high only according to the
logic equation x<0>y<0> + (x<1> + x<2>)y<1>.  Thus, an incorrect
switching activity occurs due to the charge sharing event.

      To counteract this problem, pmos precharge devices are
generally added to the circuit to pull nodes "q0" and "q1" during the
precharge cycle of the circuit operation.  This, then, removes the
charge sharing possibility.  That is, if the same input condition as
above occurs, then nodes "q0" and "q1" will be high as well as node
"int", so no charge redistribution can occur.  A diagram of this
circuit technique is shown in Fig. 2.  Note that an alternative
solution to the problem is to use nmos devices for the precharge as
shown in Fig. 3.

      However, in CMOS-SOI technology, most of the parasitic
capacitance on nodes "q0" and "q1" is removed.  That is, the majority
of the capacitance on these nodes arises from the diffusion area
created by the nmos transistors "I3" and "I4" (for node "q0") and
"I5", "I6", and "I7" (for node "q1").  In bulk technology, this
capacitance is generally quite large.  However, in SOI technology,
this capacitance is reduced by at least 2/3, leaving only 1/3 of the
parasitic capacitance.  Consequently, the precharge of the internal...