Browse Prior Art Database

Operating System Format Time Reduction

IP.com Disclosure Number: IPCOM000123081D
Original Publication Date: 1998-May-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

Kohno, M: AUTHOR [+4]

Abstract

Disclosed is a device microcode for providing a method of reducing time to format a media. Time needed for formatting a device becomes longer in proportion to increase capacity of the device. Our hypothetical read cache method is treaded verified area as hypothetical cached area. And a device can immediately return a completion when Read Verify Command points the cached area. Read Verify Command almost occupies all the time for formatting operation. Therefore the execution time for formatting is drastically reduced. 1. A hypothetical read cache method 2. Pseudo Read Verify Mode on a device 3. A function of changing modes between Pseudo Read Verify Mode and normal mode.

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Operating System Format Time Reduction

      Disclosed is a device microcode for providing a method
of reducing time to format a media.  Time needed for formatting a
device becomes longer in proportion to increase capacity of the
device.  Our hypothetical read cache method is treaded verified area
as hypothetical cached area.  And a device can immediately return a
completion when Read Verify Command points the cached area.  Read
Verify Command almost occupies all the time for formatting operation.
Therefore the execution time for formatting is drastically reduced.
  1.  A hypothetical read cache method
  2.  Pseudo Read Verify Mode on a device
  3.  A function of changing modes between Pseudo Read Verify
       Mode and normal mode.

   We prepare Pseudo Read Verify Mode.  This mode enables a
hypothetical read cache method.  The cache method is identical to a
current read cache but there are three differences between them.  One
is the cached data is not actually exists on the buffer.  Two is the
hypothetical cached range will be hold after power off.  These mean
only the cached range which is between a start LBA (logical block
address) and an end LBA is registered, and maintained only to check
if the Read Verify Command points the range or not, and data itself
is not needed because of no data transfer for the Read Verify.  The
other is no actual self-cache-range-extending operation because of
the hypothetical read caching.  For example, all area...