Browse Prior Art Database

Build-in Self Test Circuit for Fast Analog Digital Converter

IP.com Disclosure Number: IPCOM000123117D
Original Publication Date: 1998-May-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Tanaka, H: AUTHOR [+3]

Abstract

A program is disclosed that our build-in self test circuit with Phase-Locked Loop circuit and data stored circuit can be tested Analog Digital Converter which requires faster sampling clock than clock of logic tester.

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Build-in Self Test Circuit for Fast Analog Digital Converter

   A program is disclosed that our build-in self test circuit
with Phase-Locked Loop circuit and data stored circuit can be tested
Analog Digital Converter which requires faster sampling clock than
clock of logic tester.

   Functional test of Analog Digital Converter in logic IC
(integrated circuit) is limited in the maximum clock speed of
tester.  A tester cannot apply faster clock than itself to Analog
Digital Converter and cannot check the digital data outputs of the
fast speed.  Our self test circuit generates required fast clock by
Phase-Locked Loop circuit and stores fast digital data in the data
stored circuit.

   Figure shows IC with Analog Digital Converter and our self
test circuit.  Tester inputs reference clock to Phase-Locked Loop.
Output of Phase-Locked Loop is connected to the clock port of Analog
Digital Converter and data stored circuit.  Digital outputs of Analog
Digital Converter are connected to the data port of data stored
circuit.

   Phase-Locked Loop circuit multiplies reference clock from
tester and apply it to Analog Digital Converter and data stored
circuit.

   Data stored circuit are composed of shift registers.  The
width of shift registers is same as Analog Digital Converter output
bit range and the depth of shift registers is same as required
sampling points.  Digital outputs of Analog Digital Converter are
connected to the first stage of the shift registers in parallel...