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Built-in Self Test Circuit with PLL(Phase-Locked Loop) Circuit

IP.com Disclosure Number: IPCOM000123120D
Original Publication Date: 1998-May-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 4 page(s) / 115K

Publishing Venue

IBM

Related People

Mori, Y: AUTHOR [+3]

Abstract

Disclosed is a built-in self test (BIST) circuit which has a phase-locked loop (PLL) circuit as a clock signal generator, and is embedded in an integrated circuit (IC) chip for testing a circuit block or all of the circuits in the IC. The BIST with PLL enables high-speed testing of on-chip circuit blocks such as memory macros even when the clock supplied by an external tester such as an LSI (Large Scale Integration) tester is not fast enough for the functional and AC(performance) testing of the circuit blocks.

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Built-in Self Test Circuit with PLL(Phase-Locked Loop) Circuit

   Disclosed is a built-in self test (BIST) circuit which has
a phase-locked loop (PLL) circuit as a clock signal generator, and is
embedded in an integrated circuit (IC) chip for testing a circuit
block or all of the  circuits in the IC.  The BIST with PLL enables
high-speed testing of on-chip circuit blocks such as memory macros
even when the clock supplied by an external tester such as an LSI
(Large Scale Integration) tester is not fast enough for the
functional and AC(performance) testing of the circuit blocks.

   Recent semiconductor technologies allow high speed
functional macros with more than 100MHz cycle speeds in a chip.
These high speed macros include SRAM macros, ROM macros, and others.
Conventionally some of these types of macros have been tested with
on-chip BIST circuits driven by an external clock supplied by an LSI
tester, but nowadays some high speed macros exceeds the test rate,
i.e., the inverse of the test clock cycle time, of ordinary LSI
testers.  This makes it impossible to confirm the maximum cycle
speed, or minimum cycle time, of the actual hardware, and sometimes
even the minimum cycle time defined in the specification of the macro
to be tested.

   A solution to this speed mis-match between the tester
and the macro to be tested is to combine the conventional BIST
circuit and an on-chip PLL circuit which has fast enough
free-running oscillation frequency, and control the PLL output clock
frequency with a well defined, but not always very fast, external
clock supplied by an LSI tester.  As is well known, PLL can be used
as a clock multiplication circuit, thus it can be used as a generator
of a clock signal which has a frequency of integer multiplication of
the external clock frequency.  Using this well-defined high frequency
clock generated by the PLL as the clock signal to the BIST and the
macro to be tested enables the high speed test that is impossible
with low-cost, usual speed LSI testers.  Fig. 1 shows an example of
combining a BIST and a PLL.  In this example BIST can use the
external c...