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Browse Prior Art Database

Cell Corruption Recovery

IP.com Disclosure Number: IPCOM000123125D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 152K

Publishing Venue

IBM

Related People

Webb, D: AUTHOR [+2]

Abstract

A simple but efficient way to synchronize a cell handler based on a single pulse indicating the start of a cell is described. A desynchronism could result in a cell corruption; that means a partial cell has been generated at an upper level, or the FIFO, holding the cells not yet read, has been reset. The described scheme to recover from a cell corruption is also robust against glitches which could result in a false start of cell interpretation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Cell Corruption Recovery

   A simple but efficient way to synchronize a cell handler
based on a single pulse indicating the start of a cell is described.
A desynchronism could result in a cell corruption; that means a
partial cell has been generated at an upper level, or the FIFO,
holding the cells not yet read, has been reset.  The described
scheme to recover from a cell corruption is also robust against
glitches which could result in a false start of cell interpretation.

   This cell corruption recovery design has been implemented
into an ATM cell handler, but of course it can be used in any device
handling fixed size of data called cells or chunks.  The design is
composed of  a simple Finite State Machine (FSM), a common way to
describe the behavior of a logic circuit.

   For understanding, the FSM are commonly represented by
bubbles interconnected by arrows.  A bubble is a defined state and an
arrow is a condition under which the FSM jumps from one state to an
other state.  The condition are evaluated at every machine cycle.
Thus the state transitions happen at the clock edges, that means the
FSM remains in a particular state for a least one clock cycle.

Before to describe the circuit, it is explained why it is so
advantageous to be able to recover from corrupted cells: No device
can avoid corrupted cells.  If the cell server has to restart for any
reason the transmission, it is likely that the restart would happen
in a middle of a cell.  The resulting data stream would be a first
packet of cell back to back, then a partial cell and again a packet
of cell back to back.  The trail which receives these cells must
perform the needed cell manipulation (for instance HEC calculation
and payload scrambling for ATM cells).  A common way to indicate the
cell boundaries is to associate with the first data byte (8 bits) a
ninth bit called Start-of-Cell (SOC). This scheme is used for
instance on the standardized UTOPIA bus.  In the above example, the
device connected to the UTOPIA bus checks the ninth bit to locate the
cells.  This works fine, as long as no glitches can corrupt a cell:
a glitch is a noise peak which would result in a false SOC detection.
If there was a glitch, the device would interpret this as a new cell
and the decision to resynchronize or not on that...