Browse Prior Art Database

A Method for Doing Boolean Equivalence on ECO Logic

IP.com Disclosure Number: IPCOM000123129D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 72K

Publishing Venue

IBM

Related People

Lasota, PJ: AUTHOR [+2]

Abstract

Disclosed is a method for doing Boolean Equivalency Checking (BEC) on a netlist updated through the use of Engineering Change Order (ECO). Design changes introduced at the netlist level via ECO poses a model verification problem, when using a VHDL design representation for simulation and a gate level VLSI integrated Model (VIM) representation for physical design. Usually on a design project, simulation continues after physical design has been started. If simulation uncovers a functional design problem at this stage of a design schedule, the designer has two model representations to update with the design fix. The designer changes the VHDL representation and verifies the fix in simulation. After the fix is verified, the change is introduced at the Physical Design VIM netlist level through the use of ECO.

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This is the abbreviated version, containing approximately 52% of the total text.

A Method for Doing Boolean Equivalence on ECO Logic

   Disclosed is a method for doing Boolean Equivalency Checking
(BEC) on a netlist updated through the use of Engineering Change
Order (ECO).  Design changes introduced at the netlist level via ECO
poses a model verification problem, when using a VHDL design
representation for simulation and a gate level VLSI integrated Model
(VIM) representation for physical design.  Usually on a design
project, simulation continues after physical design has been started.
If simulation uncovers a functional design problem at this stage of a
design schedule, the designer has two model representations to update
with the design fix.  The designer changes the VHDL representation
and verifies the fix in simulation.  After the fix is verified, the
change is introduced at the Physical Design VIM netlist level through
the use of ECO.  This dual update which the VHDL methodology requires
at this stage of the design project poses the problem as to whether
the VHDL simulation model and the Physical Design VIM netlist are
boolean equivalent.  In order to verify that both are equivalent,
BEC is introduced into the methodology as a check to insure that
both netlists are boolean equivalent.

   The first step of this process as described in Figure 1
on the next page is to run logic synthesis on the VHDL that was
updated with the fix.  This process will create a gate level
representation of the VHDL design change.  This gate level netlist is
then compared using BEC to the VHDL simulation model to ensure that
both are boolean equivalent.  This RLM and all of the other chip
Random Logic Macro's (RLMs) are stitched together to  form the new
updated chip level VI...