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# A High Speed Modular Exponentiation Circuit

IP.com Disclosure Number: IPCOM000123145D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 65K

IBM

Satoh, A: AUTHOR

## Abstract

Disclosed is a high-speed modular exponentiation circuit. A modular exponentiation (M**E mod N) is accomplished by repeated execution of modular multiplications (A*B mod N). As shown in Fig. 1, the modular multiplication is in turn achieved by repeated partial product addition (+/-A) and adjustment operation (+/-N, +/-2N, +/-3 N, +/-4N) alternately. When the bit in the multiplicator B is '1', addition is executed, and when the bit is '0', adjustment is done. To make time for the adjustment, in another word, to avoid consecutive additions, binary redundant form is introduced into the multiplicator. Consecutive '1' bits in B are transformed such that 1111=10000-1. On the other hand, when sequential '0' bits are encountered, addition (+/-A) can be skipped.

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A High Speed Modular Exponentiation Circuit

Disclosed is a high-speed modular exponentiation circuit.  A
modular exponentiation (M**E mod N) is accomplished by repeated
execution of modular multiplications (A*B mod N).  As shown in Fig.
1, the modular multiplication is in turn achieved by repeated partial
N, +/-4N) alternately.  When the bit in the multiplicator B is '1',
addition is executed, and when the bit is '0', adjustment is done.
To make time for the adjustment, in another word, to avoid
consecutive additions, binary redundant form is introduced into the
multiplicator.  Consecutive '1' bits in B are transformed such that
1111=10000-1.  On the other hand, when sequential '0' bits are