Browse Prior Art Database

A Method For Saving Clock Opted Logic During Physical Design

IP.com Disclosure Number: IPCOM000123150D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Lasota, PJ: AUTHOR [+2]

Abstract

Disclosed is a solution to the problem of needing to rerun clock optimization on a chip if a design change is introduced during the physical design process. When a designer needs to make a logic change to the chip after the clock optimization has been run, the schedule could be severely impacted. The clock optimization process ensures that the loading on the clock tree is balanced with respect to loads and wire length. This minimizes clock skew across the chip. If the design requires synthesis then surely the loading and names on the clock tree will change thus requiring clock optimization to be rerun. This solution will prevent the need for this.

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A Method For Saving Clock Opted Logic During Physical Design

   Disclosed is a solution to the problem of needing to rerun
clock optimization on a chip if a design change is introduced during
the physical design process.  When a designer needs to make a logic
change to the chip after the clock optimization has been run, the
schedule could be severely impacted.  The clock optimization process
ensures that the loading on the clock tree is balanced with respect
to loads and wire length.  This minimizes clock skew across the chip.
If the design requires synthesis then surely the loading and names on
the clock tree will change thus requiring clock optimization to be
rerun.  This solution will prevent the need for this.

Preparation

   This solution will ensure that all latch names remain the
same and that all clock sinks are as they were before the new logic
was added.  Since the latch names and count will not change the
current clock opted tree will not have to be changed since it is
already balanced.  The first requirement in anticipation of a logic
change to the chip is to ask all designers to add spare latches in
their critical logic units.  This change needs to be done on the
design prior to entering physical design process.  If the logic
change would require a latch to be added then the loading on the
clock tree would not change because the designer could use one of the
spare latches that already exist on the clock tree.  This prevents
changing the loading on the current clock tree.

Solution

   The second step to this solution is to ensure that the
box names of all the latches are the same.  If synthesis was run to
create the logic change then this will not be the case.  To
accomplish this a program was writt...