Browse Prior Art Database

Method for facilitating hardware debug of an LSSD chip

IP.com Disclosure Number: IPCOM000123155D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 61K

Publishing Venue

IBM

Related People

Greenfield, JD: AUTHOR [+3]

Abstract

Disclosed is a methodology to assist in bringup and debug of an LSSD chip. It requires no extra chip design effort or additional logic. The implementation uses a minimal amount of card logic and system software to examine the state of every latch in the chip at the time of failure.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for facilitating hardware debug of an LSSD chip

   Disclosed is a methodology to assist in bringup and debug
of an LSSD chip.  It requires no extra chip design effort or
additional logic.  The implementation uses a minimal amount of card
logic and system software to examine the state of every latch in the
chip at the time of failure.

   In an LSSD design there is an inherent provision for
scanning the registers to chip I/O's.  This is used for testing
purposes at the foundry.  The tools that are used for a specific
technology require that the design adheres to specific "design
rules" and that a subset of the chip I/O's are defined for scanning,
scanout, and scan clocks.  There are also additional I/O's flagged
to the tester that must be held to an on/off state during the test
(scan) process.

   This disclosure mimics the actions of the tester in order to
scan the registers out of the chip and capture the data.  The scan
data can then be assembled with a list of latch logical names.  The
result is a snapshot of the logical state of every latch in the
chip.  A designer can then examine the state of his/her logic to
help determine if the hardware contains a design bug.

   The "scan" results can also be used to initialize a software
simulation model of the the design.  This would allow a designer to
trace logical levels between latch points.  Simulation could also be
used to verify that future hardware changes will either prevent this
condition from occurring or allow the design to recover from it.

   This mechanism for scanning a chip can be very useful for
early hardware bringup.   It is guaranteed to w...