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Selectable Clock Gating Controls for Optimum Chiplet Power Reduction

IP.com Disclosure Number: IPCOM000123191D
Original Publication Date: 1998-Jun-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 6 page(s) / 170K

Publishing Venue

IBM

Related People

Carr, JD: AUTHOR

Abstract

When attempting to reduce the power consumption for a design, controls to gate clocks to the logic are most often implemented. When designing these controls to put the logic to "sleep" and then "wakeup" during certain times, an extensive number of considerations have to be made. These considerations many times appear unrelated and often cumbersome to manage.

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Selectable Clock Gating Controls for Optimum Chiplet Power Reduction

   When attempting to reduce the power consumption for a
design, controls to gate clocks to the logic are most often
implemented.  When designing these controls to put the logic to
"sleep" and then "wakeup" during certain times, an extensive number
of considerations have to be made.  These considerations many times
appear unrelated and often cumbersome to manage.

   The problem of deciding the amount and right level
of complexity for this type of logic thereby requires a more
structured system for architecting the clock gating controls.  This
disclosure identifies a process for implementing a set of controls to
enable the proper and desired level of clock gating within a chiplet
design.

   To illustrate the method for providing the right
complexity for clock gating controls, a representative piece of logic
is used to show the partitioned and structure used.  In this case,
the Inverse Quantizer chiplet, part of the MPEG2 Encoder chipset, was
used.  An overall dataflow for this chiplet is shown in the following
Figure.

   Before selecting the type and scope of the gating controls
to be implemented, the designer should identify key control points
within the design.  These points in the design would identify the
progression or sequence of operation in the design.  By identifying
these points, the gating as selected, could reference or "tap" into
the design at the points necessary  to control function.  Note it is
necessary to identify control points for both the "Sleep" and "Wake"
phases of operation.

   For this reference design,  the following control points
were identified and can be used as examples of the type of control
points needed.  These control points, unique to each design of
course, should identify the key progression of events that occur
within the design during its use.  For example, what set of events
occur independent during a defined period of time during the function
of the chiplet.

   This list, although representative for this IQ reference
design, is not to be viewed as complete for this design.  Many
additional points could/would be listed for a clock gating effort
for such a design, depending on how comprehensive the designer
wanted to be in limiting power consumption.

   For each of the control points identified, they must be
identified as either sleep or wakeup specific.  Sleep control points
identify the functional operation that defines where the logic
function can be partitioned such that after that operation is
performed that that specific area of logic can be gated off.  Wakeup
control points identify the operations that after they occur, that
that specific area of logic can be turned back on.

   Using the main partitions from the dataflow as a starting
point, 3 logical identifiers are required to create a control
matrix.  The control matrix consisted of the following in Figure 2.

   These three specific identifiers...