Browse Prior Art Database

Configurable Data Path Delay Element Utilizing a Synchronous FIFO

IP.com Disclosure Number: IPCOM000123198D
Original Publication Date: 1998-Jul-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Bannister, JP: AUTHOR [+2]

Abstract

Disclosed is a design for a reconfigurable data path delay element. The design utilizes a FIFO and counters to provide a programmable delay through a logic device.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Configurable Data Path Delay Element Utilizing a Synchronous FIFO

   Disclosed is a design for a reconfigurable data path
delay element.  The design utilizes a FIFO and counters to provide a
programmable delay through a logic device.

   In computer systems which implement multiple bus
architectures, ASIC devices are designed to control the flow of data
between the various system and IO busses.  In many cases, data is
made available to the ASIC bridge device before it can be determined
that the data must actually be transmitted to another bus.  The data
must therefore be stored in the bridge device in anticipation of the
possibility that it could be forwarded.

   A simple solution to this problem is to place multiple
stages of flip flops between the point at which data enters the
device and the point at which data can be kept or discarded.  This
simple method requires WxD flip-flop or latch devices, where W is
the width of the data path and D is the number of clock cycles that
the data must be delayed before the decision point.  This can be an
inefficient use of resources if W and/or D is large compared to the
number of logic cells available to the designer.  It is also
conceivable that for a given design, D may not be easily determined,
and it may be desirable to provide some degree of variability in the
latency of the data arrival to the decision point.

   A potentially more efficient data path delay can be
implemented with a multi-ported synchronous FIFO memo...