Browse Prior Art Database

Processor Trace Facility Enhancements

IP.com Disclosure Number: IPCOM000123199D
Original Publication Date: 1998-Jul-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 27K

Publishing Venue

IBM

Related People

Levine, FE: AUTHOR [+3]

Abstract

Providing instruction and address traces is a very important part of system tuning and future system design. Disclosed here a new approach that speeds the ability to produce instruction and data address processor traces.

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Processor Trace Facility Enhancements

   Providing instruction and address traces is a very
important part of system tuning and future system design.  Disclosed
here a new approach that speeds the ability to produce instruction
and data address processor traces.

   Many processors provide a trace facility that allows the
processor to enter in single step mode.  In this mode, after an
instruction is executed, a single step interrupt is taken.  The
information provided by the hardware at the time the single step
interrupt is taken may be used to create instruction traces.  By
using the facility described in "Processor Single Step Facility
Enhancements", IBM Technical Disclosure Bulletin, Vol. 39, No. 12,
one can relatively easily also create complete instruction and data
address traces, but at the cost of putting the processor in
single-step mode.

      Disclosed here is a new trace mode hereby called
load-store-branch trace mode.  In this mode the processor is
interrupted only when one of the bits described in "Processor Single
Step Facility Enhancements", IBM Technical Disclosure Bulletin, Vol.
39, No. 12 are set, therefore avoiding all unnecessary interrupts
and providing the fastest way possible to generate instruction and
data address traces using a processor trace facility.