Browse Prior Art Database

I2C Logic Analyzer Preprocessor

IP.com Disclosure Number: IPCOM000123201D
Original Publication Date: 1998-Jul-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Wolford, RR: AUTHOR [+2]

Abstract

This article describes a circuit used to preprocess Inter IC (I2C(1)) data. The circuit places the I2C data in a format which logic analyzers can recognize. The aids in the debugging of I2C interfaces. Prior to this disclosure, no circuit existed that prepared I2C data for use by a logic analyzer.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

I2C Logic Analyzer Preprocessor

   This article describes a circuit used to preprocess Inter
IC (I2C(1)) data.  The circuit places the I2C data in a format which
logic analyzers can recognize.  The aids in the debugging of I2C
interfaces.  Prior to this disclosure, no circuit existed that
prepared I2C data for use by a logic analyzer.

   Because of the asynchronous, synchronous, and serial nature
of the I2C (Inter IC) bus, it is impossible to view the I2C bus
cycles directly on a logic analyzer today.  Logic analyzers today
can be used in either state mode or timing, but not both.  State
mode is useful for synchronous bus cycles while timing mode is
useful for asynchronous bus cycles.

   This invention preprocesses the I2C bus cycles and presents
them to the logic analyzer in a format which the logic analyzer can
recognize.  The preprocessor detects the asynchronous START and STOP
conditions, converts synchronous I2C read and write data from a
serial to parallel format, and generates a clock for the logic
analyzer to latch in the bus cycles.  Status indicators are also
provided to indicate the state of the SCL and SDA bus signals.

   The START and STOP detection circuitry consists of two stage
latches.  For the START condition, the first latch is set when SCL
and SDA are high.  Then the second latch gets set when a high to low
transition occurs on SDA.  For STOP, the first latch is set when SCL
and SDA are both low.  Then the second latch is set when a low...