Browse Prior Art Database

Debug Capabilities for Logic Built-In Self-Test

IP.com Disclosure Number: IPCOM000123203D
Original Publication Date: 1998-Jul-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 30K

Publishing Venue

IBM

Related People

Fields Jr, JS: AUTHOR [+3]

Abstract

Disclosed is a Logic Built-In Self-Test (LBIST) controller with capability to exit the LBIST process at various points, allowing easy isolation of LBIST failures or design errors.

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Debug Capabilities for Logic Built-In Self-Test

   Disclosed is a Logic Built-In Self-Test (LBIST) controller
with capability to exit the LBIST process at various points,
allowing easy isolation of LBIST failures or design errors.

   The LBIST process begins with scanning a known initial
pattern into the logic under test.  Then, over a large number of
iterations, the clocks are single-cycled and new pseudo-random
patterns are scanned into the logic.  As new patterns are scanned
in, the logic state resulting from each single-cycle of the clocks
is captured in a signature register.  A final scan returns the logic
under test to a functional reset state.

   The LBIST controller disclosed here allows the number of
iterations of clocking and scanning to be programmable via an IEEE
1149.1 JTAG port, as well as three breakpoint bits.  When Breakpoint
bit 1 is set, the LBIST controller exits after the scan of the
initial pattern.  Breakpoint 2 causes the LBIST controller to exit
after the single-cycle in the last iteration.  Breakpoint 3 causes
the LBIST controller to exit after the scan in the last iteration,
bypassing only the scan of the reset pattern.

   By using the three Breakpoint bits, and varying the
iteration count, it is possible to capture a scan dump from the
logic under test which corresponds to the first point at which any
LBIST differences exist between successive LBIST runs on the same
chip, or among multiple chips, allowing easy isolation of failures. ...