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High Speed Clocking Design for Test

IP.com Disclosure Number: IPCOM000123209D
Original Publication Date: 1998-Jul-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Asano, T: AUTHOR

Abstract

Disclosed is a circuit design technology for applying faster clock than LSI (Large Scale Integrated circuit) tester.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

High Speed Clocking Design for Test

   Disclosed is a circuit design technology for applying
faster clock than LSI (Large Scale Integrated circuit) tester.

   Fig. 1 is the proposed design for the test.  Port A is
the mode select signal for disabling Port B signal by negative state
at Port A for Test mode.  Port B and C can be used for any purpose in
Normal mode.  In Test mode, two phased clocks as in Fig. 2 are
applied from the LSI tester.

   Port E obtains twice as fast clock from two phased ones.

   As LSI process technology is advanced, the requirement of
applying fast clock to test fast macros is stronger.  The LSI which
has PLL (Phase Lock Loop) by the application can supply fast clock
both in Normal mode and in Test mode.  But, LSI without PLL will need
some way to apply fast signal at test.  Putting PLL for test is one
way, but the proposed technique is more cost efficient than PLL.
While the LSI tester has a limitation on the maximum cycle time, it
has good accuracy on clock skew.  Taking advantage of such LSI
tester's characteristic, it is possible to make x2 clock from 2
phased clocks.

   Since the requirement on fast clock is only for test, one
of the two clock input pin can be shared for other purposes in
Normal mode.

   Fig. 1 is the proposed circuit diagram for test.  Fig. 2
is the timing chart in Test mode.  It is possible to make xN clock
from N phased clocks as far as tester allows.