Browse Prior Art Database

A Scheme of Decoupling for PGA Socket

IP.com Disclosure Number: IPCOM000123217D
Original Publication Date: 1998-Jul-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 26K

Publishing Venue

IBM

Related People

Hoang, B: AUTHOR [+4]

Abstract

Disclosed is a scheme of decoupling for point grid array (PGA) socket. This design helps to reduce current spikes, faster current supply to CPU and is inexpensive to manufacture.

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A Scheme of Decoupling for PGA Socket

   Disclosed is a scheme of decoupling for point grid array
(PGA) socket.  This design helps to reduce current spikes, faster
current supply to CPU and is inexpensive to manufacture.

   The board designer used voltage regulator (VR) to step
down voltage from 3.3 volts to 2.5 volts or some times lower.  They
need to step down voltage because the core of the CPU requires to run
with lower voltages than the external devices.

   Power PC processor in PGA package have  core voltage pins
near the center of the array.  It is difficult to place decoupling
capacitors near the voltage pins, and to solve this problem, there
are two unique designs.
  o  The socket is designed to stand off slightly from the
      printed circuit board such that decoupling capacitor
      can be placed under the socket.
  o  A unique footprint for the surface mount technology 0603
      capacitor was designed which allow the capacitor to be
      placed between voltage and ground pins under the socket.

   The assembly process is to reflow the capacitors before the
socket is inserted.  The 0603 footprint also may be placed on the
back side of the printed circuit board if additional decoupling is
needed.