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Method and Apparatus for System and Tester Controlled Variable Voltage/Impedance

IP.com Disclosure Number: IPCOM000123245D
Original Publication Date: 1998-Jul-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Douskey, SM: AUTHOR [+2]

Abstract

Nest chip designs, required to match various processors, must be adaptable and testable for various voltage and impedance I/O. The hardware to switch variable voltage and impedance must not only be controlled in the system environment, but also must fit into the test structure. The hardware configuration and test pattern sequence described here meets these needs.

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Method and Apparatus for System and Tester Controlled Variable Voltage/Impedance

   Nest  chip  designs, required to match various processors,
must be adaptable and testable for various voltage and impedance
I/O.  The hardware to switch variable voltage and impedance must not
only be controlled in the system environment, but also must fit into
the test structure.  The hardware configuration and test pattern
sequence described here meets these needs.

   The figure shows a logical configuration that allows both
test and system control of the variable voltage input to one or more
I/O cells.  A variable impedance input is controlled the same way.

   The select and control latches are Scan Only and are
initialized to 0's in the system environment.  The TEST signal is
also 0, allowing the system controlled latches to control the
variable voltage (VV) inputs to the drivers.  Note that in the
system mode the VV_IN chip input is ignored.  The figure also shows
how this signal can be used as a functional output in this case.

   At the tester, it is important that the voltage and
impedance remain constant throughout the test, as tester setup
changes can be difficult.  It is also important that all
combinations can be set up at the tester.

   While scanning the TEST signal is a 1, and the VV_IN signal
controls the impedance and voltage values.  Once scanning is
complete the TEST input can change (required in some test modes,
i.e., testing the functionally shared outp...