Browse Prior Art Database

A Dedicated Comparator to Detect the Minimum Value in a Neural Network at the Earliest

IP.com Disclosure Number: IPCOM000123269D
Original Publication Date: 1998-Aug-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Iruela, J: AUTHOR [+2]

Abstract

The main task of a neural network is to classify or recognize an input vector presented to it. To perform that task, the network has been previously trained with a number of selected prototypes, each one representing a class or category. This training is called the learning process. At the recognition process, one of the best criteria is to find the prototype (stored in the network during the learning) which is the closest to the input vector presented to the network. For the ZISC* chip family, a dedicated circuit labelled 'Minimum Circuit' has been described in US Patent 5,717,832. Several ZISC chips are connected together through an open drain bus to allow the computation of the nearest located prototype by the chip itself and not by an external device. The drawback is bus slowness because of delays in output drivers.

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A Dedicated Comparator to Detect the Minimum Value in a Neural Network
at the Earliest

   The main task of a neural network is to classify or
recognize an input vector presented to it.  To perform that task, the
network has been previously trained with a number of selected
prototypes, each one representing a class or category.  This training
is called the learning process.  At the recognition process, one of
the best criteria is to find the prototype (stored in the network
during the learning) which is the closest to the input vector
presented to the network.  For the ZISC* chip family, a dedicated
circuit labelled 'Minimum Circuit' has been described in US Patent
5,717,832.  Several ZISC chips are connected together through an open
drain bus to allow the computation of the nearest located prototype
by the chip itself and not by an external device.  The drawback is
bus slowness because of delays in output drivers.  For that reason,
only 1 bit is considered to be right at each cycle, and the feedback
value needed to compute the remaining bits is coded on N-1 bits.
That means for a N bit bus, N machine cycles are needed to compute
the minimum for the worst case data values.  But most of the time the
minimum is found after N/3 cycles because the worst case data values
for the distance can only be found at the beginning of the training
process where the "space" is not yet entirely occupied by neurons.

   A real time recognition performance improvement would
result if a device could detect when the minimum has been found.
Such information is given by a comparator connected between the
inputs and the outputs of the register storing...