Browse Prior Art Database

Stepped Pyramid Chip Stack

IP.com Disclosure Number: IPCOM000123293D
Original Publication Date: 1998-Sep-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 5 page(s) / 140K

Publishing Venue

IBM

Related People

Kulesza, JD: AUTHOR [+2]

Abstract

Disclosed are several structures to increase the silicon circuit density (for a given die foot print) by stacking chips together in a way that maximizes I/O density in a minimum profile carrier package with the potential extension for direct chip attach to a circuit panel.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Stepped Pyramid Chip Stack

   Disclosed are several structures to increase the silicon
circuit density (for a given die foot print) by stacking chips
together in a way that maximizes I/O density in a minimum profile
carrier package with the potential extension for direct chip attach
to a circuit panel.

   Chips are stacked together in layers that build up to form
a stepped pyramidal shape.  Refer to Figure 1.  Each chip (11) would
form a step (12) on the pyramid and each die size would be slightly
smaller to allow for external connection via C4 bonds (13) around the
perimeter of each chip.  The chips would be bonded together using
epoxy (14) in a special fixture designed to hold the chips in
relative alignment until the epoxy has cured.  C4 sites on the
perimeter of each chip mate with connect sites (15) on the chip
carrier (16).  Interconnection from chip to chip would be
accomplished via circuit traces on the chip carrier.  The chip
carrier is built up in layers that mate with the steps of the chip
pyramid.  Each layer would consist of a flex circuit (17), epoxied
to a layer of prepreg (18) in a separate process and then each level
is bonded together with another layer of epoxy (19) in a final
assembly step.  From chip to carrier to connection points, circuit
traces on the flex layer connect to BGA sites (20) elsewhere on the
carrier or to other chip levels on the same carrier.  A solder ball
(21) must be placed on each mating site on the chip or chip carrier
and is melted in a bonding process to complete chip to carrier
connection.  A high temperature solder ball on the bottom BGA (22)
may be necessary to support the weight of the chip stack.

   The chip pyramid is inverted and inserted into the "socket"
of the chip carrier.  Refer to Figure 2 which shows a finished
assembly.  Even heating of the chip and carrier prior to mating is a
concern that may be overcome with good control of IR.  In the
resultant assembly the top of the top chip could be flush with top of
the substrate.  The chip is exposed for attachment of a heat sink or
for wire bond on the top.

   Figure 3 shows a bottom view of the chip stack and available
C4 sites.

   A hole (41) in the bottom of the substrate to expose the
bottom chip (42) for better IR reflow of the C4 pads.  See Figure 4.
However, this can be beneficial for heat dissipation while the chip
stack is running and to allow access to the bottom chip for further
wirebonding (43) for the chip to the carrier on the bottom.

   Good control of the mech...