Browse Prior Art Database

High Speed Latch for Digital Systems

IP.com Disclosure Number: IPCOM000123316D
Original Publication Date: 1998-Sep-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 5 page(s) / 217K

Publishing Venue

IBM

Related People

Bjorksten, AA: AUTHOR [+3]

Abstract

Circuitry is disclosed for latching a signal in a dynamic circuit. The latch circuitry includes: an input circuit for producing a first signal; a precharge circuit for precharging the first signal; an inverter coupled to the precharge circuit and the input circuit for receiving the first signal and outputting a second signal, wherein no time delay occurs between the inverter and the precharge and input cirucits, wherein the second signal can be either a high or low signal; and a clamp which holds the second signal during a subsequent precharge of the first signal, wherein the second signal is the output signal.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 26% of the total text.

High Speed Latch for Digital Systems

   Circuitry is disclosed for latching a signal in a dynamic
circuit.  The latch circuitry includes: an input circuit for
producing a first signal; a precharge circuit for precharging the
first signal; an inverter coupled to the precharge circuit and the
input circuit for receiving the first signal and outputting a second
signal, wherein no time delay occurs between the inverter and the
precharge and input cirucits, wherein the second signal can be either
a high or low signal; and a clamp which holds the second signal
during a subsequent precharge of the first signal, wherein the second
signal is the output signal.

   FIG. 1 is a schematic showing key functional elements of
the latch circuit 60 of the present invention.  The latch circuit 60
includes a logic circuit 62 connected to a latch element 64.  The
output state of the logic circuit 62 is latched in the latch element
64.  The logic circuit 62 includes a dynamic logic block 14, a
half-latch 66, a clock 22, a first transistor 68, and a second
transistor 70, which are all conventional.  The latch element 64
includes a selective inverter 72, an inverter 74, a first transistor
76, and a second transistor 78, which are all conventional or
constructed from conventional elements.

   The selective inverter 72 is used to selectively gate a
state received from the logic circuit 62.  The output of the
selective inverter 72 is connected to the inverter 74 whose output is
connected to the gate of the first transistor 76, and the gate of the
second transistor 78.  The first transistor 76, and the second
transis tor 78 work together to selectively maintain a state at the
output of the latch circuit 60 in response to a complementary state
at the input of the inverter 74.  The input of the inverter 74 is the
output of the selective inverter 72.

   The half-latch 66 includes an inverter 12 and a transistor
20.  The output of the inverter 12 is connected to the gate of the
transistor 20 at the node 18.  The source of the transistor 20, and
the input of the inverter 12 are connected at the node 16.  Within
the logic circuit 62, the node 16 is connected at a node between a
pair of transistors that form the inverter 12.  Output from the
inverter 12 is connected to the gate of a PMOS transistor 20.  The
drain of the transistor 20 is connected to a high source of
potential, and the source of the transistor 20 is connected to at the
node 16.  When the node 16 is high, output from the inverter 12 is
low.  The low state on the gate of the transistor 20 turns the
transistor 20 on, connecting the node 16 to a high source of
potential.  This holds the node 16 high.  When a low state is present
at the node 16, a high state is present at the output of the inverter
12, which turns off the transistor 20 and isolates the node 16 from
the high source of potential through the transistor 20.

   The output of the dynamic logic block 14, and the source
of the fir...