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Contactless On-chip AC I/O Wrap Test

IP.com Disclosure Number: IPCOM000123342D
Original Publication Date: 1998-Sep-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 5 page(s) / 149K

Publishing Venue

IBM

Related People

Diebold, U: AUTHOR [+2]

Abstract

Abstract As the construction of high pin count (> 1000 signals) COBRA contactors reaches nearly impossibility (not to mention the costs) it becomes absolutely vital to realize a method to characterize all chip I/O's with low pin count test equipment.

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This is the abbreviated version, containing approximately 43% of the total text.

Contactless On-chip AC I/O Wrap Test

   Abstract

   As the construction of high pin count (> 1000 signals)
COBRA contactors reaches nearly impossibility (not to mention the
costs) it becomes absolutely vital to realize a method to
characterize all chip I/O's with low pin count test equipment.

   This paper describes a technology independent way to test
the I/O parametrics (drive capability and voltage levels) of
bidirectional books on high pin count chips without actually
connecting these I/O's to individual tester channels during
chip-/wafer-test.

   A pass device in the I/O books, connecting to a 'Driver
Test Bus', which on its turn connects to one tester channel allows
sequentially testing of all bidirectional books.  The pass devices
must be controlled by a latch chain, where only 1 latch is active at
a time.

   Introduction

   Chips with high pin counts are designed such that all
internal logic can be controlled and tested via a limited number
(e.g. 64) of so called primary inputs and outputs.  This test is
named 'the internal test'.  The inputs and outputs connect directly
to individual tester channels and can be single inputs, single
outputs or bidirectional books (bidi's).  Pins above this limit must
be bidi's with Boundary Scan (BSC-) latches.  With this configuration
the driver and receiver path can be tested on conductivity without
actually contacting the C4-pad,thus allowing a 'reduced pin count
testing'.  A logical 'one', set into the driver's boundary scan
latch, will propagate into the receiver's latch via the pad (the same
goes for a logical 'zero').

   Due to the high impedance property of the (receiver-)input
stage it is an obvious disadvantage of this testing method that the
specified drive capability of the driver output stage presently under
test can NOT be tested.  The specified drive capabilities can only be
tested by connecting every bidi to a separate tester channel.
  Figure 1: Typical Bidirectional Book in CMOS Technology

   As shown in Fig. 1 , the driver part of the bidi
essentially consists of a BSC latch, logic for controlling the gates
of the driver output stage (not shown in Fig. 1), and the p- and
n-device of the driver output stage connecting to the C4-pad (P11,N1
1).

   The receiver part of the bidi consists of a pulldown (PD)
transistor, controlled by a Receiver Inhibit (RI) signal, and the p-
and n-device of the receiving input stage (P12,N12) connecting to the
same pad.  The receiver stage itself is connected to the BSC latch
via a control logic (not shown in Fig. 1).

   Contactless on-chip AC I/O wrap test

   This chapter describes a method of testing the driver part
for the specified drive capability as well as the data path for the
receiver part of the bidi book.  For this reason two extra
components must be added to the 'standard' bidi book, shown in
Figure 1.
  o  One AND gate (G11 ..  Gn1 for n bidi's, see below)
  o  A pass device latch, resulting in a scan cha...