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Defect Map with Defect Category, Electrical Test Result & Chip Layout

IP.com Disclosure Number: IPCOM000123368D
Original Publication Date: 1998-Oct-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 25K

Publishing Venue

IBM

Related People

Satoh, K: AUTHOR

Abstract

A method for mapping defects on a semiconductor wafer is disclosed. It is the first mapping method that optical defects, their classified category and electrical failures are aligned on a map template. It can be decided whether an optically found defect causes electrical failure or not, at a glance. It is also seen how much each defect classification correlates with electrical test. The method makes the analysis of the semiconductor defect more easier.

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Defect Map with Defect Category, Electrical Test Result & Chip Layout

   A method for mapping defects on a semiconductor wafer is
disclosed.  It is the first mapping method that optical defects,
their classified category and electrical failures are aligned on a
map template.  It can be decided whether an optically found defect
causes electrical failure or not, at a glance.  It is also seen how
much each defect classification correlates with electrical test.  The
method makes the analysis of the semiconductor defect more easier.

   The new defect mapping procedure is following:
  (1) To prepare a wafer template with chip layout as well
      as fine layout within a chip.
  (2) Optical defects found by defect monitor tool such as
      KLA2135 and Tencor-AIT are plotted on the template using
      the coordinates given by the monitor tool.
  (3) Classification category with visual inspection is also
      superposed on the defect with its own Mark.
  (4) Electrical fail address is transferred to physical
      coordinates of a wafer and is marked on the map.
  (5) Then electrical fail and optical defect and category are
      combined on a same wafer map.