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MEMS sensor and ASIC flip-chip bump integration

IP.com Disclosure Number: IPCOM000123387D
Publication Date: 2005-Apr-04
Document File: 4 page(s) / 103K

Publishing Venue

The IP.com Prior Art Database

Related People

Bishnu P. Gogoi: AUTHOR [+3]

Abstract

A method of flip chip assembly of a MEMS sensor device with a wafer level protective cap on an ASIC (Application Specific Integrated Circuit) is described. The technology of forming a wafer level cap for a MEMS accelerometer is described using the example of a High Aspect Ratio Accelerometer. The benefits of the assembly integration are discussed along with an example process flow.

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MEMS sensor and ASIC flip-chip bump integration

Bishnu P. Gogoi, Mike E. Chapman and Ray M. Roop

Freescale Semiconductor Inc.,

2100

E. Elliot Rd,

MD

EL 720,

Tempe

,

AZ

85284

Contact: Bishnu.Gogoi@freescale.com, phone: 480 413 8836, fax: 480 413 4453

Abstract:

A method of flip chip assembly of a MEMS sensor device with a wafer level protective cap on an ASIC (Application Specific Integrated Circuit) is described. The technology of forming a wafer level cap for a MEMS accelerometer is described using the example of a High Aspect Ratio Accelerometer. The benefits of the assembly integration are discussed along with an example process flow.

                                                            Introduction

MEMS sensors such as accelerometers need a hermetic cap in a molded package that protects it from the environment. The plastic transfer molding process generates a high pressure that can be in the range of a thousand pounds/square inch. The hermetic cap must be capable of withstanding the transfer molding pressure or be isolated from it. The hermetic cap also protects the MEMS device from sawing and other pre-molding assembly operations.

The technique of flip chip bumping can be used advantageously to protect the cap from the pressures of the plastic molding during the assembly process. In addition, there are other benefits that can be derived from the flip chip bumping of the sensor die to the corresponding ASIC (Application Specific Integrated Circuit). Since the sensor die and the IC are formed on two different wafers and different manufacturing processes, it is possible to have independent yields with reduced process complexity. Also, by using a wafer level cap to protect the sensor, the die size can be considerably reduced. Since the electrical connections are made using bumps instead of wire bonds in the case of a stacked die configuration, it is possible to reduce the parasitic capacitance.

Process flow description

The formation of a wafer level cap for an accelerometer is described for a High Aspect Ratio SOI (Silicon on Insulator). After the sensor structure sensor is formed in the SOI using DRIE (Deep Reactive Ion Etching) and other well known process steps, a second polysilicon cap layer is then deposited above a second PSG sacrificial layer and holes are defined for release.  The device is then released using vapour phase etch without any stiction. The etch holes are closed with a sealing layer and pressure inside the cavity is defined during the sealing process to satisfy damping specifications. A picture of a completed device with the wafer level cap is shown in Fig. 1.0.

Fig.1.0. SEM view of the accelerometer with a wafer level cap

The integration of the completed accelerometer sensor with an IC...