Browse Prior Art Database

Multiple hit cache

IP.com Disclosure Number: IPCOM000123425D
Original Publication Date: 1998-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 2 page(s) / 84K

Publishing Venue

IBM

Related People

Oba, N: AUTHOR [+2]

Abstract

Disclosed is a mechanism for implementing an on-chip instruction cache for VLIW processors. In conventional VLIW processors, the supply bandwidth of the instruction from the instruction cache is one of the dominant factors in the processor performance. The disclosed mechanism expands the bandwidth by making use of the cache's set-associativity.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 65% of the total text.

Multiple hit cache

   Disclosed is a mechanism for implementing an on-chip
instruction cache for VLIW processors.  In conventional VLIW
processors, the supply bandwidth of the instruction from the
instruction cache is one of the dominant factors in the processor
performance.  The disclosed mechanism expands the bandwidth by
making use of the cache's set-associativity.

   A VLIW instruction consists of two or more subinstructions,
which can be executed in parallel.  In the disclosed mechanism, one
VLIW instruction is divided into N subsections, which could be one or
more subinstructions.  Each subsection is stored in the same set but
different way of the instruction cache.  Figure 1 is a typical VLIW
instruction, which consists of four subinstructions.  When the
instruction cache is four-way set-associative, the instruction is
stored in the same set of the cache, as shown in Figure 2.  It should
be noted that the tag fields of the ways have the same address, A.
The LRU field of the ways has the same value, 0, for the use of
replacement.  Figure 2 also shows that VLIW instruction B, which
consists of two subinstructions, is stored in another set of cache.

   When an instruction fetch takes places, the cache searches
whether it has the copy or not, as a conventional cache does.  The
disclosed cache, however, can hit one or more ways in the same set.
In the example in Figure 2, the cache hits are detected in all four
ways.

   The features of the mechanism are: (...