Browse Prior Art Database

High Performance Multistage Pass Gates

IP.com Disclosure Number: IPCOM000123452D
Original Publication Date: 1998-Nov-01
Included in the Prior Art Database: 2005-Apr-04

Publishing Venue

IBM

Related People

Durham, CM: AUTHOR [+2]

Abstract

Disclosed is a method for improving the propagation delay through multistage pass gates. Implementing logic with multistage pass gates has advantages such as small area, low power, relatively high performance and simplicity of implementation.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High Performance Multistage Pass Gates

   Disclosed is a method for improving the propagation delay
through multistage pass gates.  Implementing logic with multistage
pass gates has advantages such as small area, low power, relatively
high performance and simplicity of implementation.

   A prior art implementation with two pass gates connected
in series is shown in Fig. 1.  INV1 serves as a driver for the gate
of QF3 which in conjunction with QF4 and QF5 forms the first of two 3
way multiplexors connected in series.  To facilitated a simplified
simulation environment for this circuit the sources and gates of QF4
and QF5 are grounded.  In a normal system environment both
transistors would be driven similar to QF3.  Reset p-channel
transistor QR1 precharges node data_1 to VDD when its input is low.
When data_1 goes high it turns on transistor QS1 via inverter QS2 and
QS3.  This half latch structure maintains the high level of data_1
once reset has gone low.  The second multiplexor stage consists of
QF6, QF7 and QF8.  Reset device QR7 and half latch circuit QS5, QS6
and QS7 perform the functions of QR1, QS1, QS2 and QS3 in the first
multiplexor stage.  The Gate of QF6 is driven by INV2, the source is
connected to the drains of QF3, QF4 and QF5 and its drain is
connected to the drains of QF7 and QF8 and the input of output
driver INV4.  Sources and drains of QF7 and QF8 are also grounded in
this diagram for the same reasons as discussed for transistors QF4
and QF5.  Likewise their source and gates are driven by similar
circuits as QF6 under normal circuit operation.  For completeness
inverter INV4 is shown to drive LATCH0 which is connected to the
inverter consisting of QF14 and QF15 and Capacitor C500 represents a
general circuit load.  The reset clock input is connected to inverter
INV3 receiving the inverted reset clock.  When reset is high the
circuit is in the reset state.  Evaluation takes place when reset
goes low.  Reset takes place while the output latch is inactive.
Since the default level of data_1 and data_2 is high after reset,
only the high to low transition of the circuit is of interest fo...