Browse Prior Art Database

Redundant Register Routing

IP.com Disclosure Number: IPCOM000123453D
Original Publication Date: 1998-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Duron, MC: AUTHOR [+3]

Abstract

Disclosed is a method by which a designer may use pre-defined functions and data paths as alternate paths when one path becomes unavailable. The components used to accomplish inter-processor communication will be described. A description of normal operation will follow. Finally a discussion of the problems, solutions and benefits will be documented.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Redundant Register Routing

   Disclosed is a method by which a designer may use
pre-defined functions and data paths as alternate paths when one
path becomes unavailable.  The components used to accomplish
inter-processor communication will be described.  A description of
normal operation will follow.  Finally a discussion of the problems,
solutions and benefits will be documented.

   The system environment consists of several components,
the Processor complex and the I/O (Input/Output) system.  The
processor or processors may be thought of as a global entity since
they process instructions for the entire system.  Figure 1 may be
used a reference.

   The I/O system is made up of I/O subsystem components.  In
this case the I/O subsystem is scalable and therefore partitioned
into manageable logical and physical components.  A system may be
scaled up by simply adding on another I/O subsystem component or
scaled down by deleting I/O components.

   A Local Processor resides within each I/O subsystem
component.  The Local Processor is designed to monitor and report
faults to the System Processor(s).  This function is accomplished
with the Fault Register, Mask Register, and the Cache Register area.
The Fault register is used by the Local Processor to report faults to
the System Processor(s) by writing a logical "1", which will in turn
cause a system interrupt to occur.  This is one inter-processor
communication path.  Another communication path is the Mask Register.
This register is used by the System Processor to signify to the Local
Processor the receipt of the fault.  The last communication path for
the fault monitoring function is the Cache Register area.  This may
be used to pass any type of fault related information or parameters
from the Local I/O subsystem to the System level.

   The System Processor and Local Processor use yet another
communication path to accomplish VPD (Vital Product Data) gathering.
During normal operation, the system firmware will gather VPD as part
of its boot process making it available to applications running on
the system.

   A typical fault monitoring scenario will now be
described.  The Local Processor detects a parity check and writes a
logical "1" to the Fault Register.  A system interrupt occurs.  The
interrupt handler will now read the Fault Register to determine the
source of the fault.  This is possible since the Fault Register or
Registers are predefined to associate a particular fault with a
particular bit position in the group of r...