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Browse Prior Art Database

Method for Compressed Debug Data Accesses

IP.com Disclosure Number: IPCOM000123454D
Original Publication Date: 1998-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 3 page(s) / 98K

Publishing Venue

IBM

Related People

Sriram, PS: AUTHOR

Abstract

As the frequency targets and complexity of IC designs keep increasing, it becomes more and more difficult to debug and eliminate faults in them. Special circuitry is implemented to provide visibility to key areas of operations and functional parameters. The volume of such debug information is quite tremendous and is usually narrowed down to a few signals of interest. As the architectural implementation increases from 32bits to 64bits and beyond, the width of such interesting data also increases proportionately. There are pad, package and design limitations that restrict the growth of the available width of such debug information. This proposal seeks to alleviate such an information bottleneck by providing a means of compression of debug/trace data. This is explained in detail in Fig.

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Method for Compressed Debug Data Accesses

   As the frequency targets and complexity of IC designs
keep increasing, it becomes more and more difficult to debug and
eliminate faults in them.  Special circuitry is implemented to
provide visibility to key areas of operations and functional
parameters.  The volume of such debug information is quite
tremendous and is usually narrowed down to a few signals of
interest.  As the architectural implementation increases from 32bits
to 64bits and beyond, the width of such interesting data also
increases proportionately.  There are pad, package and design
limitations that restrict the growth of the available width of such
debug information.  This proposal seeks to alleviate such an
information bottleneck by providing a means of compression of
debug/trace data.  This is explained in detail in Fig. 1,
"Description of debug/trace compression method".  The advantages of
such an implementation are obvious, with data compression more data
can be pumped through in the same amount of time.  Real-time or near
real-time debug information can be obtained even with a much lowered
transfer rate than that of the chip/device under test.  Such a scheme
is needed if we are to successfully debug and deliver designs of very
high complexity and frequency.

   One method for implementing such an architecture would be
to use a simple huffman encoding algorithm for performing the
compression.  This is explained in more detail in the Fig. 2,
"Compression engine implementation".

   Based on historical probability information, a compression
data lookup table can be programmed as shown in Fig. 2, "Compression
engine implementation ".  Depending on the byte of data being
encoded, the table gives the output data to be sent out.  Since the
output code length is variable, and due to the nature of the huffman
coding algorithm, high...