Browse Prior Art Database

Translation Control Entry Performance Enhancement by Association with a Device's Arbitration Level

IP.com Disclosure Number: IPCOM000123457D
Original Publication Date: 1998-Nov-01
Included in the Prior Art Database: 2005-Apr-04
Document File: 1 page(s) / 50K

Publishing Venue

IBM

Related People

Buckland, P: AUTHOR [+5]

Abstract

In systems where 32-bit I/O devices must access 64-bit address spaces, it is necessary to have some sort of translation mechanism in the bridges to translate the 32-bit to 64-bit address. If this is not to be a fixed translation (which has many restrictions) then a dynamic method must be used, and such is the case in PowerPC platforms. In these systems a Translation Control Entry (TCE) is associated with each 4KB block of address space and this determines which I/O bus 4KB page will access which System Memory 4KB page. These TCEs are generally fetched when the devices first accesses a new page. The TCEs themselves are stored in System Memory, and there is a latency associated with the fetching of the TCE. This latency reduces I/O performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 61% of the total text.

Translation Control Entry Performance Enhancement by Association
with a Device's Arbitration Level

   In systems where 32-bit I/O devices must access 64-bit
address spaces, it is necessary to have some sort of translation
mechanism in the bridges to translate the 32-bit to 64-bit address.
If this is not to be a fixed translation (which has many
restrictions) then a dynamic method must be used, and such is the
case in PowerPC platforms.  In these systems a Translation Control
Entry (TCE) is associated with each 4KB block of address space and
this determines which I/O bus 4KB page will access which System
Memory 4KB page.  These TCEs are generally fetched when the devices
first accesses a new page.  The TCEs themselves are stored in System
Memory, and there is a latency associated with the fetching of the
TCE.  This latency reduces I/O performance.

   Additionally, the TCEs buffers in a bridge are generally
managed as a pool of resources, and when an I/O device gets off the
bus and another one gets on, if the resource which is holding the TCE
is needed to buffer a new TCE, the old TCE is thrown out.  If the
previous I/O device then gets back on the bus and needs the TCE that
it was using before, that TCE needs to be fetched again, possibly
replacing another TCE that will be needed at a future time.  This
throwing away of TCEs that will be needed again is wasteful of not
only the I/O devices' time waiting on the latency of the TCE fetch,
but also on the system perform...