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Low Power CMOS Logic Level Shifter with Protection Against Hot Carrier Degradation

IP.com Disclosure Number: IPCOM000123536D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 1 page(s) / 62K

Publishing Venue

IBM

Related People

Bunch, RL: AUTHOR [+2]

Abstract

In voltage translation buffer circuits the entire power supply voltage (ex. 3.3V) can appear across certain transistors. In a process optimized for 2.5V logic, this may present a hot carrier problem. Hot carrier effects can cause reliability problems (e.g., threshold voltage shifts) when the drain to source voltage of a MOSFET exceeds a certain limit. In the circuit described here in this limit is approximately 2.8 volts. While this circuit was implemented to interface from 2.5V to 3.3V, it is also suitable for interfacing other voltage levels such as 1.8V to 2.5V.

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Low Power CMOS Logic Level Shifter with Protection Against Hot Carrier
Degradation

   In voltage translation buffer circuits the entire
power supply voltage (ex. 3.3V) can appear across certain
transistors.  In a process optimized for 2.5V logic, this may
present a hot carrier problem.  Hot carrier effects can cause
reliability problems (e.g., threshold voltage shifts) when the drain
to source voltage of a MOSFET exceeds a certain limit.  In the
circuit described here in this limit is approximately 2.8 volts.
While this circuit was implemented to interface from 2.5V to 3.3V, it
is also suitable for interfacing other voltage levels such as 1.8V to
2.5V.

   The circuit as depicted in Fig. 1 and described herein
solves both the problems of current consumption and hot carrier
degradation that are associated with level translation schemes of
this type.  The input logic level is 2.5 volts and the output level
is 3.3 volts.  The circuit is implemented such that the voltage
across all the transistors is never greater than 2.5 volts (the
specified range of the target technology).  This is accomplished by
splitting the output voltage across multiple devices, in turn,
eliminating the hot-carrier concern.  The circuit also uses positive
feedback to eliminate currents caused by transistors which are
partially on.  In the circuit of Fig. 1, the input signal is applied
directly to the gate of M4 and is inverted before being applied to
the gate of M8.  PFETS M2 and M6 and NFETS M3 and M7 are guard
devices that are connected to g...