Browse Prior Art Database

Interconnecting Structure Between a N Ports Switch Module and a Backplane Connector

IP.com Disclosure Number: IPCOM000123566D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 4 page(s) / 141K

Publishing Venue

IBM

Related People

Ouazana, C: AUTHOR [+2]

Abstract

Disclosed is a method to interconnect high speed digital signals on a printed circuit board (PCB) on which are mounted Very Large Scale Integration (VLSI) active components and connecting devices to a backplane on which are plugged the PCB.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

Interconnecting Structure Between a N Ports Switch Module and a Backplane
Connector

   Disclosed is a method to interconnect high speed digital
signals on a printed circuit board (PCB) on which are mounted Very
Large Scale Integration (VLSI) active components and connecting
devices to a backplane on which are plugged the PCB.

   The increasing required bandwidth of communication systems
leads to high density and high speed active components performing
switching functions.  The amount of digital inputs/outputs terminals
of VLSI modules reaches several hundreds to meet the required
bandwidth.  Since the VLSI modules are mounted on pluggable cards,
the connectivity between VLSI terminals and card connector raises the
problem of interconnecting several hundreds of high speed signals
from active devices, generally located in one part of a card, to
connector devices, located in another part of a card.

   High density VLSI components are characterized by a matrix
pattern of I/O terminals as in Pin Grid Array or Ball Grid Array
packages.  Connector I/O terminals are characterized by patterns
arranged in a more linear way.

   A frequently used PCB design consists in a set of VLSI
components located in the center part of the board and a serie of
connectors located at one edge of the card.  This kind of design
allows the card to be plugged in a rack in the same way as a book in
a shelf.

   The card designer has a given set of constraints for
component placement.  If the function is a 16 ports switch, one can
expect that there are 16 identical connector submacros laid out on
the card physical design and the machine structure forces the
connector submacros to be numbered according to a particular
sequence to fit the wireability constraints of the board on which is
connected the board under design.

   Let's take the example of a port numbering from 0 to 15 in
ascending order from the right side of the connector to the left
side.

   A connector submacro is composed of several bundles of
signals.  Some may be related to a receive function, some other may
be related to a transmit function.  If there are two modules,
labelled 0 and 1, we may also have bundles connected to one
particular module.  The following deals with four types of
connexions, RCV0, XMT0, RCV1, XMT1, each bundle using a dedicated
card layer, so that there are four independent layers to be
designed.  The bundle could be a group of 4, 8 or 16 nets, depending
on the bus structure.

   A structured routing will take benefit of the modularity
of the functions and of the existing geometrical characteristics
(symetry, translation, rotation) of the VLSI module and connector
devices.

   The I/O assignment of the module is very often liable
to be customized according to the logic functions to be performed.
Once the power supply and other reserved I/O are assigned, there is
some freedom to allocate some package regions to some particular
functions.

   In the case of a 16 por...