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A Single-layer Polysilicon EEPROM Memory Cell using Diffusion Gate

IP.com Disclosure Number: IPCOM000123585D
Original Publication Date: 1999-Jan-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Sasaki, K: AUTHOR

Abstract

Disclosed is a single-layer polysilicon EEPROM memory cell using diffusion gate as control gate. Fig.1 is the top view of the cell. Fig. 2, Fig. 3, and Fig. 4 are the cross-section of the cell. Write/erase operation is explained by Fig. 2. The polysilicon floating gate couples to the N+ diffusion as capacitive coupling. Write operation is performed by channel hot electron injection. (Drain side of TR1 : 5V, the diffusion under TR2 : 10V) Erase operation is carried out by Fowler-Nordheim tunneling current. (Source line : 10V, the diffusion under TR2 : 0V) Fig. 5 is the process flow of this cell.

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A Single-layer Polysilicon EEPROM Memory Cell using Diffusion Gate

   Disclosed is a single-layer polysilicon EEPROM memory cell
using diffusion gate as control gate.  Fig.1 is the top view of the
cell.  Fig. 2, Fig. 3, and Fig. 4 are the cross-section of the cell.
Write/erase operation is explained by Fig. 2.  The polysilicon
floating gate couples to the N+ diffusion as capacitive coupling.
Write operation is performed by channel hot electron injection.
(Drain side of TR1 : 5V, the diffusion under TR2 : 10V) Erase
operation is carried out by Fowler-Nordheim tunneling current.
(Source line : 10V, the diffusion under TR2 : 0V) Fig. 5 is the
process flow of this cell.

   The EEPROM cell has two advantages as follows.  1.  As the
process is very simple, it takes low cost.  2.  Because of using a
single-layer polysilicon, the device reliability is more excellent
than usual two-layer polysilicon EEPROM.