Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

PCI Bus Address Translation Logic

IP.com Disclosure Number: IPCOM000123760D
Original Publication Date: 1999-Apr-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Bonds, TL: AUTHOR [+3]

Abstract

Two PowerPC 60x to PCI bridge chips cannot be connected to the same PCI bus because of the way 60x to PCI address mapping is done in the bridge chip per the PowerPC architecture. This poses a problem if one wants to design a system with multiple 60x processors connected through a PCI interface.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 97% of the total text.

PCI Bus Address Translation Logic

   Two PowerPC 60x to PCI bridge chips cannot be connected to
the same PCI bus because of the way 60x to PCI address mapping is
done in the bridge chip per the PowerPC architecture.  This poses a
problem if one wants to design a system with multiple 60x processors
connected through a PCI interface.

   Disclosed is a method which implements address translation
which allows for more than two 60x to PCI bridges in the system,
while using industry standard modules.  From a system prospective,
this allows delivery of a highly parallel system using relatively
little expense.  In this implementation, one uses industry standard
shallow PCI adapters, standard PCI to host bridges and standard
processors.  In addition to expense, this solution allows faster time
to market.  The development of enhancements is facilitated by
separation of function between I/O adapters, translation logic, host
bridges, and processors.

   The solution is the right place to add hardware to fix
these problems inside the 60x/PCI bridge.  However, current bridge
designs do not incorporate such a function; therefore, external xlt
logic is needed.  The xlt logic is added between the 60x to PCI
bridge to translate addresses on the fly.

   Figure 1 shows where the xlt logic is placed in a typical
60x system.  Figure 2 shows a timing diagram of how the logic works.
Figure 3 is a block diagram of the logic showing the xlt logic
implemented using FET switches to do bu...