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Efficient Checking Method for Control Logic

IP.com Disclosure Number: IPCOM000123818D
Original Publication Date: 1999-May-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Gerwig, G: AUTHOR [+2]

Abstract

Disclosed is an efficient method for checking a control logic without doubling it. For a bunch of control signals a bunch control signal (Bunch_Ctrl) is generated which can be used for checking each exclusive bunch signal.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 84% of the total text.

Efficient Checking Method for Control Logic

   Disclosed is an efficient method for checking a control
logic without doubling it.  For a bunch of control signals a bunch
control signal (Bunch_Ctrl) is generated which can be used for
checking each exclusive bunch signal.

   For using the new checking method the control logic has
to be structured in a way to collect control signals which control a
certain multiplexer together with a bunch such that all control
signals to that multiplexer are exclusive.

   For checking of single bit failures usually a bunch compare
signal (Bunch_Cmpr) is used.  The value of Bunch_Cmpr is obtained by
counting the number of the active control signals in the bunch.  If
there is no hardware failure the value of Bunch_Cmpr is '0' or '1'.
Alternatively a multiple 'XOR' function can be used.

   In the present checking method an additional bunch control
signal (Bunch_Ctrl) is generated by a separate logic.  The value of
Bunch_Ctrl is equivalent to a logic 'OR' of the single control lines
of a bunch.

   Bunch_Ctrl is compared to Bunch_Cmpr.  Both signals must be
equal, otherwise the bunch check signal (Bunch_Check) gets active.

   The figure shows a control logic with the present bunch
checking method embedded in a hierarchical structure check.  A
pipeline active signal (Pipeline_Active) which is typically used in a
control logic is active if at least one of the multiplexers (A,B) in
that pipeline is activated.  This will force at lea...