Browse Prior Art Database

Neuron Autonomous Logic Circuits

IP.com Disclosure Number: IPCOM000123868D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 8 page(s) / 377K

Publishing Venue

IBM

Related People

Incertis Carro, F: AUTHOR

Abstract

A novel architecture for building spatially distributed, delay insensitive, self-assertive combinational logic systems and asynchronous, self-clocked, self-latching, autonomous sequential logic systems by interconnecting a new class of self-assertive "neuron-like" components is disclosed.

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Neuron Autonomous Logic Circuits

   A novel architecture  for building spatially distributed,
delay insensitive, self-assertive combinational logic systems and
asynchronous, self-clocked, self-latching, autonomous sequential
logic systems  by interconnecting a new class of self-assertive
"neuron-like" components is disclosed.

   NEURON LOGIC CIRCUIT (NLC) A generic combinational logic
circuit, Neuron Logic Circuit (NLC), is firstly disclosed (see Fig.
1), formed by a Dendrite Logic Circuit (DLC) receiving a plurality of
"dual-rail" NLC LOGIC Inputs (dendrites), an Axon Logic Circuit (XLC)
generating a plurality of "dual rail" NLC LOGIC Outputs (axons) and
performing a diversity of combinational logic functions from
dendrites to axons by means of a Soma Logic Circuit (SLC) or soma, in
such a form that the NLC is fully insensitive to the different delays
among its own constituent parts (DLC, SLC, XLC) and to the different
delays on the connections from axons of each NLC to dendrites of any
other NLC in a (complex) network of NLCs and self-asserts the
completion and the validity of their logic operations.  Dendrites and
axons are all "dual-rail", i.e. each input (dendrite) and output
(axon) has two rails, named Left (L) and Right (R).  Status
conventions for dendrites and axons are the following:
  DUMMY: (0 0);  VALID "OFF": (0 1);  VALID "ON": (1 0) ;
  INVALID: (1 1)

   A NLC operates in such a form that when all dendrites
are VALID the NLC asserts completion of logic operations and
indicates this fact when all axons become VALID.  If all dendrites
are DUMMY, all axons become DUMMY; any other combination of
not-all-dendrites VALID or not-all-dendrites DUMMY turns all axons to
the INVALID state.

   Fig. 1 shows the NLC implemented by using dual-rail logic
circuits built from the class of Transfer Logic Cells (TLCs) that
have been disclosed in (1) TLCs are combinational logic circuits for
performing elementary logic operations between a dual-rail input and
a dual-rail output from at least one control terminal selecting a
mode of operation among four logic modes, namely: PASS, LEFT, CROSS
and RIGHT or, from two non-logic modes, namely: ISOLATION and
TRANSPARENT.  (1) also discloses a method for implementing logic
functions by cascading a plurality of TLCs forming  an assemblage of
TLCs in which conducting paths are established such as the paths are
dependent upon the logic states present on the control terminals and
of the logic function carried out by the assemblage, the logic states
present on the dual-rail output of any circuit of the assemblage,
located either at the end point of paths or at intermediate points of
paths, being usable for driving other assemblages of the same or more
TLCs adapted to carrying out the herein above method of implementing
logic functions.  (1) further discloses all types of possible arrays
comprising a plurality of elements, each of them housing one orm ore
TLCs adapted to carrying out the her...