Browse Prior Art Database

Automated Protocol Generation of Coherence Protocol Logic

IP.com Disclosure Number: IPCOM000123900D
Original Publication Date: 1999-Jun-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Glasco, D: AUTHOR

Abstract

Disclosed is a technique that can automate the generation of logic for a cache coherence protocol for a cache coherent, non-uniform memory access (CC-NUMA) system given a table description of the protocol. Typically, the protocol is specified in English and transformed into logic by a logic designer. But unfortunately, the cache coherence protocols for a CC-NUMA system are typically quite complicated, and every time the protocol changes, the logic, which is usually specified in a high-level design language (HDL), must be changed by hand. To overcome this difficult and time consuming process of converting an English description of a cache coherence protocol into a logic description that can be synthesized, the following technique can be used.

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Automated Protocol Generation of Coherence Protocol Logic

   Disclosed is a technique that can automate the generation
of logic for a cache coherence protocol for a cache coherent,
non-uniform memory access (CC-NUMA) system given a table description
of the protocol.  Typically, the protocol is specified in English and
transformed into logic by a logic designer.  But unfortunately, the
cache coherence protocols for a CC-NUMA system are typically quite
complicated, and every time the protocol changes, the logic, which is
usually specified in a high-level design language (HDL), must be
changed by hand.  To overcome this difficult and time consuming
process of converting an English description of a cache coherence
protocol into a logic description that can be synthesized, the
following technique can be used.  This technique uses the logic
minimization program ESPRESSO and two standard UNIX tools, SED and
CAT.

   Initially, the cache coherence protocol is fully specified
in a table format that consists of two sections: an input and an
output section.  The generation of a low level logic description,
which can be directly synthesized, can be performed in several
steps, as shown in the Figure.  First, the protocol is specified in a
typical design document.  Next, an ASCII dump of the protocol table
is generated and parsed by a C code program that converts the text
table into an ESPRESSO equivalent input format.  This file is then
reduced by ESPRESSO and converted to a V...