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Method for Scanning a CPU Reset State via a Test Access Port

IP.com Disclosure Number: IPCOM000123932D
Original Publication Date: 1999-Jul-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 1 page(s) / 30K

Publishing Venue

IBM

Related People

Dixon, R: AUTHOR [+3]

Abstract

Where a test port does not make available the CPU Hard Reset signal, the signal may be required for additional applied circuitry to correct some known machine operation. Rather that making wire changes to the circuit board, the Test Access Port is used to poll the CPU state and determine if a Hard Reset has occurred.

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Method for Scanning a CPU Reset State via a Test Access Port

   Where a test port does not make available the CPU Hard
Reset signal, the signal may be required for additional applied
circuitry to correct some known machine operation.  Rather that
making wire changes to the circuit board, the Test Access Port is
used to poll the CPU state and determine if a Hard Reset has
occurred.

   This technique sets a special  bit in the  CPU, via the
JTAG interface.  This bit is special in 2 ways.  First, the bit is
cleared only by Hard Reset, and second, the bit is in a status
register that may be continuously polled via the JTAG interface even
when the CPU is operational.

   The algorithm is as below:
  1.  Apply hard reset (hreset) and jtag reset (treset)
  2.  Deassert treset
  3.  Issue cop freeze command
  4.  Deassert hard reset (processor will be clock stopped here)
  5.  Scan LSRL to set an abist status bit in the
      processor logic.
      The latches to set would be:
        ZAA_604.DAA.DT0.DWLA.NAN0.L2(0:3) = x'F'
        ZAA_604.DAA.DT0.DWLA.NAN1.L2(0:3) = x'F'
  6.  Issue a RESUME Cop command.
      (the processor should start)
  7.  Issue a BISTCLR cop command (code x'A6')
  8.  Issue a STAT ESP command.
      you should see the norepair bit set (bit-1 set)
  9.  Keep repeating 7 and 8.  A hard reset will clear
      the latches that were set by the LSRL scan and you
      should see this in the c...