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IP.com Disclosure Number: IPCOM000123943D
Original Publication Date: 1999-Aug-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 3 page(s) / 127K

Publishing Venue

IBM

Related People

Appinger, J: AUTHOR [+3]

Abstract

When testing VLSI chips, a huge set of test patterns has to be forwarded to the chip's latches and the logical response of the chip has to be recorded. The test patterns have to be stored in the tester's memory. As the number of logical functions on a chip increases continuously, so does the amount of test patterns required for testing said logical functions. In order to store the tremendous amounts of test patterns, each tester would have to comprise a huge memory.

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   When testing VLSI chips, a huge set of test patterns has to
be forwarded to the chip's latches and the logical response of the
chip has to be recorded.  The test patterns have to be stored in the
tester's memory.  As the number of logical functions on a chip
increases continuously, so does the amount of test patterns required
for testing said logical functions.  In order to store the tremendous
amounts of test patterns, each tester would have to comprise a huge
memory.

   In most cases, though, a test pattern can be compressed
significantly, because only a subset of the test pattern's bits is
actually relevant for the logical function to be tested.  These
bits, which will be referred to as "care-bits" in the following,
have to be specified explicitly.  The rest of the test pattern's
bits may be chosen at random, because the test result does not
depend on these bits.

   A typical test pattern with a length of 32 bits might look
like this: Bits 0, 3, 12, 13 and 25 are care bits, whereby bits 0, 3
and 13 have to be equal to "1" and whereby bits 12 and 25 have to be
equal to "0".  The rest of the bits may be chosen at random, because
the test result does not depend on their value.

   In order to minimize the memory space needed, only a "seed"
of the final test pattern is stored, which is then forwarded to a
pattern generator.  The seed comprises less bits than the test
pattern, but it comprises more bits than the number of care bits in
the final test pattern.  The task of the pattern generator is to
expand the seed to the full test pattern by reproducing the correct
values of the care bits and by filling all the other bit positions
with random values.

   This is shown in Fig. 1.  The "seeds" are part of the
stored pseudo TITES code  (TITES stands for "technology independent
test evaluation system"), which is forwarded to the scan-in of the
generator.  The generator produces the pseudo TITES patterns, which
contain the predetermined zeros and ones at the correct care bit
positions.  This can be seen in Fig. 1: The pseudo TITES pattern
matches the fault relevant pattern in all the bit positions that
contain care-bits.  A typical pattern generator comprises at least
one LFSR (Linear Feedback Shift Register).

   In...