Browse Prior Art Database

"Single Cycle Chip-to-Chip Multiplexer"

IP.com Disclosure Number: IPCOM000123994D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 6 page(s) / 192K

Publishing Venue

IBM

Related People

Goecke, G: AUTHOR [+4]

Abstract

Modern computer-systems need bus-structures which are capable of transferring Gigabytes per second between processor and memory, processor and I/O-adapter or, in case of a multiprocessor-system, between processor and processor. Wide busses and low cycle times are known means to achieve a high bus-bandwidth.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 45% of the total text.

"Single Cycle Chip-to-Chip Multiplexer"

   Modern computer-systems need bus-structures which are
capable of transferring Gigabytes per second between processor and
memory, processor and I/O-adapter or, in case of a
multiprocessor-system, between processor and processor.  Wide busses
and low cycle times are known means to achieve a high bus-bandwidth.

   Another requirement, especially for multiprocessor systems,
is a low latency.  Every time when a processor issues a command on
the bus, the processor has to wait for a response from another
processor (i.e. bus snooping) or status of an I/O -adapter (i.e.
communications) or status from memory (i.e. memory-error,
key-misses).

   Due to packaging limitations (wire-length|) and high
bus-frequencies, modern multiprocessor-systems use
switching-networks or crossbar-switches to connect processors, I/O
adapters and memory controllers together.  All these switches have to
use multiplexers to distribute incoming commands/data to all other
bus-participants.

   State of the art shared memory implementations use dotted
busses, where 10 and more bus-participants are dotted on a single
physical bus, and switching networks which need some cycles to
distribute the signals to the receiving ports (i.e. PCI-bridges in
the workstation environment).

   The following chapters describe a chip-to-chip multiplexer
for a high-speed bus-switching network.  It is a single-cycle mux
which does not add any logic delay to the external paths.  The main
idea of this invention is to neutralize the chip-to-chip clock skew
with the multiplexer delay.

   State of the art multiplexers

   Usually a single-cycle chip-to-chip multiplexer is
designed in one of the two ways shown in Fig. 1.  Both types of
multiplexers have one big disadvantage: The delays of receiving and
driving nets are no longer symmetric.  For mux "a" the receiving net
has a longer delay, for mux "b" the driving net.

   Path Considerations

   The entire path between driving chip, switching network
and receiving chip is shown in Fig. 2 for the case that multiplexer
"a" is used.

   The complete path delay in Fig. 2 has the following
components:

   Cycle 1:
  o  Slave-Latch propagate (driving chip)
  o  Drive-Net-Receive delay (driving chip to switching chip)
  o  Mux delay (switching chip)
  o  Master-Latch setup (switching chip)
  o  additional components like "noise" and "chip-to-chip clock
     skew"

   Cycle 2:
  o  Slave-Latch propagate (switching chip)
  o  Drive-Net-Receive delay (switching chip to receiving chip)
  o  Master-Latch setup (receiving chip)
  o  additional components like "noise" and "chip-to-chip clock
     skew"

   The "chip-to-chip clock-skew" between different chips in
a multiprocessor-system is about 10 % to 20 % of the cycle time (in
case a cycle time of 6.5 ns is assumed, the chip-to-chip clock skew
will be about 1.2 ns).  The mux delay is typically the same (about 1
ns).

   Hidd...