Browse Prior Art Database

Precise Interrupt Handling for Out-of-Order Instruction Execution

IP.com Disclosure Number: IPCOM000123996D
Original Publication Date: 1999-Sep-01
Included in the Prior Art Database: 2005-Apr-05
Document File: 6 page(s) / 198K

Publishing Venue

IBM

Related People

Boehm, DH: AUTHOR [+4]

Abstract

A new interrupt processing method for out-of-order executed instructions on superscalar processor systems is introduced. It provides precise interrupt reporting as required for a lot of computer architectures.

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This is the abbreviated version, containing approximately 39% of the total text.

Precise Interrupt Handling for Out-of-Order Instruction Execution

   A new interrupt processing method for out-of-order executed
instructions on superscalar processor systems is introduced.  It
provides precise interrupt reporting as required for a lot of
computer architectures.

   State of the Art

   The problem to supply precise interrupts is shown in:
"POWER and PowerPC" Shlomo Weiss, James E. Smith

   The method shown in this document requires in-program-order
instruction processing in the execution units (pipelines); precise
interrupt handling is achieved by synchronizing the different
pipelines.

   The proposed new method has no restrictions: instructions
may be executed out-of-order on different pipelines, and identical
pipelines may be duplicated in the system.  Instructions may be
implemented in microcode or completely hardwired.

   Invention

   The interrupt handling described differs in many aspects
from the state of the art implementations.  Basically, the following
three sequential steps are taken to provide precise interrupts:
  1.  Stop instruction processing in all pipelines
  2.  Switch from out-of-order to in-order instruction execution
  3.  Restart instruction processing at the architecture state
      in order to hit the interrupt again.

   There is no general requirement to execute all of the
above steps; some of them may be omitted, depending on the actual
state of the processor system and the type of the interruption.

   The proposed method is based on superscalar processor
environment comprising the following building blocks:
  1.  Instruction dispatcher
  2.  Register rename unit
  3.  Reservation station
  4.  Execution units
  5.  Reorder buffer
  6.  Retire control
  7.  In-order list

   Interrupt architecture

   Basically, interrupts may be grouped into 3 categories:
  1.  Synchronous interrupts generated at the end of an
      instruction called TL-exc generated in the instruction's
      last cycle.  A typical example would be an overflow
      exception.
  2.  Synchronous interrupts generated at the begin of an
      instruction called T0-exc generated in the first cycle.  A
      typical example would be an invalid instruction format.
  3.  Asynchronous interrupts such as timer, input/output
      etc. interrupts.

   Step 1: Stop Instruction Processing in all Pipelines

   As an example, an out-of-order computer system comprising
three pipelines - two integer units and one branch unit - is
discussed.

   Whenever a synchronous interrupt (type TL or T0) is
detected in one of the 3 pipelines, instruction processing stops
immediately in the pipeline where the interrupt was found, and the
other pipelines complete (if possible) execution of the current
instruction.  When all pipelines have stopped instruction
processing, the whole processor system enters the trap level in
order to start evaluation of the interrupt.  This...