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Method to Form a Sub-lithographic, Multi-threshold, Self-aligned Stack-Gate Structure

IP.com Disclosure Number: IPCOM000124034D
Original Publication Date: 2005-Apr-06
Included in the Prior Art Database: 2005-Apr-06
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Abstract

We teach a concept to suppress leakage current by forming stack-gate structure using spacer gate. Furthermore, we propose a method to form at least one pair of stack gate structure, where first device has the same or substantially different threshold than the other device. The combination of spacer gates and angled implant yields the best result of changing threshold voltage of one device of the stack-gate pair.

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Method to Form a Sub-lithographic, Multi-threshold, Self-aligned Stack-Gate Structure

Here, we demonstrate process steps to form a dual Vt stack NMOS device side by side with a PMOS device. Based on the same spirit, other combinations of stack-gate structure can be fabricated.

    Fig. 1, Device isolation; e.g., shallow trenched 30 are formed on a semiconductor p-type substrate 10. A pad oxide 20 and well junction 40 are all done using conventional process.

    Fig. 2, After replacing the pad oxide with a gate dielectric, a NMOS device having a gate poly 55 capped with nitride layer 60 and sidewall spacers 45 are formed in the p-type substrate with a proper channel doping. The NMOS device has a source/drain doping area 50. Lightly doped junction (not shown) can be formed optionally. The dimension (the length) of the NMOS device can be equal to or greater than the minimum ground rule dimension of current technology. A PMOS device with a corresponding gate poly 80 and source/drain junction 70 are formed in the N-well region. Up to this step, everything is done by using conventional process.

    Fig. 3, A block-out mask 95 is used to cover the PMOS device before conducting an angled implant 90 on one predetermined side of the NMOS structure to form halo structure 100 on one predetermined junction. In order to avoid the complexity of implant and layout orientation restrictions, one can design a mask 95 to cover the PMOS as well as partial of the NMOS where no implant is required. This would restrict minimal gate length of the NMOS device so to accommodate mask alignment tolerance. The halo doping concentration is adjusted so that after doping, the threshold voltage of the NMOS device will rise to a predetermined level. The amount of angled implant, i.e., energy and dose, is tuned so that it will change the Vt of one of the pair stack-gate structure uniformly.

    Fig. 4, An insulating material 110 is deposited and planarized via chemical mechanical polishing and stop at the gate nitride cap layer.

    Fig. 5, A same mask 120 as used in the Fig-3, can be used to open up the NMOS area 125.

Fig. 6, To selectively remove the cap nitride 130.

    Fig. 7, To selectively perform poly spacer etch to form poly spacer 140 and 150. Sometimes, it may be necessary to fo...