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Methodology Utilizing ECC to Lower Standby Voltage

IP.com Disclosure Number: IPCOM000124037D
Original Publication Date: 2005-Apr-06
Included in the Prior Art Database: 2005-Apr-06
Document File: 6 page(s) / 75K

Publishing Venue

IBM

Abstract

Low power SRAM operation is enabled by using ECC to correct the cell failures when the SRAM voltage is scaled to low voltages. A hybrid solution is described which will allow the SRAM to maintain maximum performance during the high performance mode, but when shifted to the low performance- low power mode will insert a Error Correction Code (ECC) circuit element in the SRAM data flow to correct the SRAM bits uniquely failing at the lower voltage.

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Methodology Utilizing ECC to Lower Standby Voltage

Background

One the challenges associated with technology scaling is the increase in threshold voltage variation, due to random dopant fluctuations on the narrow width transistors. This is of particular concern for the SRAM cell, which utilizes the narrowest devices and has a limited tolerance for device mismatching. The SRAM cell is a bi-stable element which is susceptible to loosing its state when noise sources (Vt, Leff, Weff, and power supply variations to name a few) become too large. Static Noise Margin (SNM) describes how tolerant a given SRAM cell is to these noise sources. The curves below show how the SRAM cell Node A responds when Node B is forced and overlays this with the response of Node B when Node A is forced. The largest square that fits within these curves represents the cells static noise margin. A cell with '0' SNM will not hold its state, but usually more margin is needed; a value of 150-200mV of SNM was traditionally considered good enough to allow the cell to tolerate normal process variations. However, with the increase in threshold variations, this convention is being challenged, and increasing static noise margin is considered mandatory.

1.4

Static Noise Margin Static Noise Margin

1.2

1

0.8

0.6

0.4

0.2

0

0 0.2 0.4 0.6 0.8 1 1.2 1.4

1

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Vdd Vdd

Vdd Vdd

Vdd Vdd

Vdd Vdd

T5 T6

A B

T5 T6

A B

T1 T2

T3 T4

T1 T2

T3 T4

6 Device SRAM cell 6 Device SRAM cell

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SNM decreases with Operating Voltage SNM decreases with Operating Voltage

1.40E+00

1.20E+00

1.2V
1.0V

1.00E+00

Node B (V)

8.00E-01

6.00E-01

4.00E-01

2.00E-01

0.00E+00

0 0.2 0.4 0.6 0.8 1 1.2 1.4

Node A (V)

This is especially important a lower supply voltages because the cell static noise margin decreases when the operating supply is reduced, increasing the probability of a cell failure. The following graph illustrates how the cells predicted fail rate increases as the voltage is reduced. At 1.2 volts the statistical modeling of the cells static noise margin predicts that only
.08 cells will fail for every million SRAM bits. This increases to 10 fails per million when the voltage is reduced to .8V, making it very difficult to scale down the voltage to save power.

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SRAM Stability Trends PPM vs. Vdd Impact of Vt variation

1.00E+03

1.00E+02

1.00E+01

m

1.00E+00

pp

1.00E-01

1.00E-02

0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

Vdd (V)

Stability Fails

Operating the SRAM at these lower voltages is further exasperated by its increased sensitivity to leakage defects. At low voltages the cell becomes very sensitive to small gate oxide defects challenging both yield and reliability.

Gate oxide leakage for failure vs. Vdd

0.035

0.03

)0.025

(mA

ate flip

0.02

defect sensitivity

0.015

ig

0.01

0.005

0

0.7 0.9 1.1 1.3 1.5

Vdd

Summary

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