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Method for reconfigurable silicon in a package

IP.com Disclosure Number: IPCOM000124059D
Publication Date: 2005-Apr-07
Document File: 5 page(s) / 45K

Publishing Venue

The IP.com Prior Art Database

Abstract

Disclosed is a method for reconfigurable silicon in a package. Benefits include improved functionality, improved performance, and improved application flexibility.

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Method for reconfigurable silicon in a package

Disclosed is a method for reconfigurable silicon in a package. Benefits include improved functionality, improved performance, and improved application flexibility.

Background

              Conventionally, several problems exist in silicon chip development, including the following:

•             Long turn around time for silicon development

•             Expensive reticles for silicon

•             Multiple components for system application

•             Expensive and long development cycle of system on a chip (SoC) applications

              Conventional solutions to the problems include the following:

•             Using field programmable gate arrays (FPGAs) or field programmable analog arrays (FPAAs)

•             Structured application-specific integrated circuits (ASICs) with multiple logic blocks placed on a single chip and customized by redesigning the last few metal layers

              FPGAs have been used in many integrated circuit (IC) products, such as programmable memories and programmable logic devices (PLDs) or FPAAs for programmable analog devices (see Figure 1).

General description

              The disclosed method is multiple reconfigurable chips in a package for different modules or system applications. The method can be extended to highly mixed radio frequency (RF), analog, digital, and memory mixed component or system applications with several functional blocks and programmability implemented in each single silicon. Different combinations of silicon, including entire modules or systems, can be included in a single package. The silicon can be rebonded or reprogrammed to meet different application requirements.

              The key elements of the method include the following:

•             Combination of different chips assembled in a single package

•             Can be rebonded or reprogrammed

•             Can be used for different modules or systems applications

•             Product customization only at the package level

Advantages

              The disclosed method provides advantages, including:
•             Improved functionality due to enabling product customization at the package level
•             Improved functionality due to enabling chip rebonding or reprogramming

•             Improved functionality due to enabling different chips, such as FPGAs and FPAAs, to be assembled in a single package

•             Improved performance due to using multiple logic blocks and programmability

•             Improved application flexibility due to enabling the chip to be used for different modules or systems applications

Detailed description

              The di...