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Improved System for Accessing JTAG Components on Remote Devices

IP.com Disclosure Number: IPCOM000124128D
Original Publication Date: 2005-Apr-08
Included in the Prior Art Database: 2005-Apr-08
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Abstract

In computing systems, a host classically accesses a JTAG component on a remote device by bit-banging (controlling) individual JTAG signals via a simple register or I/O port on the remote device. When the interface with this bit-banging register has high latency and large amounts of data are involved the performance of this bit-banging technique can be become unacceptably slow. The solution is to provide function on the remote device which can transact with a host at a higher level (e.g. - byte or packet level) and subsequently translate this into the required low level JTAG signal control.

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Improved System for Accessing JTAG Components on Remote Devices

Accessing a JTAG component on a remote device is classically performed by bit-banging (writing/reading) individual bits of a special register or I/O port on the remote device. This effectively allows a host to manipulate and sense the individual JTAG control signals which interface with the JTAG device of interest. The drawback is that if the interface between the host and the remote device has a lot of latency (high overhead per transaction) and a large quantified of data is involved this can take excessively long to complete. Such a system is depicted in the following drawing:

Register or I/O Port

TCK

TMS TDO

TDI

JTAG

Device

Host

High latency interface

JTAG transactions can be broken down into three basic phases - set up, data transfer, and termination. The set up and termination phases are relatively short and are best performed using the classical bit-banging approach. However, the data transfer phase can be very long and repetitive and lends itself well to automation. By automating the JTAG data phase it is possible to greatly reduce the number of transactions on the high latency host interface resulting in a substantial performance improvement.

Such a system which provides for automation of the JTAG data phase is depicted in the following diagram and operates as follows:

Host initially sets up the JTAG component by bit-banging in the classical fashion.

Host writes a byte of data the a special d...